Showing papers on "Decimal published in 1985"

Intermediate Cognitive Organizations in the Process of Learning a Mathematical Concept: The Order of Positive Decimal Numbers

Abstract: This investigation found that children use three implicit and incorrect rules when comparing decimal numbers and that these rules are intermediate levels of response in the process of learning decimal numbers. The rules are intermediate in that: (a) the frequency of their use by children decreases from the fourth grade to the seventh grade; and (b) when a child is able to give a correct answer to the comparison of two decimal numbers, it is possible to induce use of the rules by giving the child more than two numbers to compare. These findings are interpreted as evidence that intermediate cognitive tools, which respond successfully to most of the tasks encountered early in learning, continue to coexist with more advanced tools.

A Model of Students' Decimal Computation Procedures

Abstract: A model that describes the construction and execution of decimal computation procedures is presented. Our hypothesis is that students compute by relying solely on syntax-based rules; semantic knowledge has no effect on performance. To test the claim, a model is developed in which computation procedures are viewed as chains of component symbol manipulation rules. The model assumes that students acquire through instruction the individual rules that achieve subgoals in the computation process. The task for the procedural system is to select rules that satisfy each subgoal in sequence. The model specifies the rules of the system and identifies the syntactic features of the task that affect the selection of individual rules at each decision point. It then predicts the relative difficulty of decimal computation items and predicts the procedural flaw that will occur most frequently on each item. Written test and interview data are presented to test the predictions. Concluding comments discuss the nature of students' computation procedures, compare the model with other models of computation performance, and outline how the model might inform instruction. In this article, we present a model of how students compute with decimal numbers. The model consists of symbol manipulation rules that we believe are precisely the rules students acquire, store, and execute to compute with decimals. The purpose of the model is to describe the nature of students' computational skills and to demonstrate the extent to which students' computation performance is procedurally based. Our hypothesis is that by the time students reach upper elementary school their behavior on many mathematical tasks can be described in syntactic rather than semantic terms. Sufficient evidence has accumulated over the past 10 years to suggest that students' behavior on mathematical tasks changes in important ways as they

Information transmission system

Abstract: 1,235,481. Signalling by audio-frequencies. BRITISH AIRCRAFT CORP. Ltd. 12 March, 1969 [19 Dec., 1967], No. 57589/67. Heading G4H. [Also in Division H4] In a system for signalling between a central station and a number of remote gun stations by radio telephone or over telephone lines the central station has a microphone and an encoder adapted to accept a decimal input and produce a binary coded output the "1" and "0" bits of which are represented by two audio-frequency tones, means being provided to transmit either the output from the microphone or the output from the encoder and means at the receiver to reproduce either speech or the original decimal input. The decimal input, from a computer for a keyboard, is applied to the encoder and a switch passes it to the transmission circuit. The signals are gated into a shift-register in the encoder under the control of clock pulses. A counter gives a signal when the message is complete to switch the transmission back to the microphone. At the gun station the two frequencies are separated by filters, the output of the "1" filter being applied to a call recognition circuit which enables the decoder. This comprises a shift register into which the incoming serial signals are shifted under the control of clock pulses derived by combining the outputs of the "1" and "0" filters. The output of the shift register is recoded from binarycoded-decimal form into decimal form and displayed on indicators showing the azimuth and bearing to which the gun is to be laid. Speech signals are reproduced on a speaker.

A Method for the Precise Measurement of the Difference between Two Low Frequencies

Abstract: A method is presented for measuring the difference between two low frequencies with high resolution. The method is based on multiplying the two incoming frequencies by a large factor and then using a BCD up/down counter to store and display the resulting frequency difference. To achieve a resolution of n decimal places, the multiplication factor must be 10n and the decimal point must be placed n digits to the left of the least-significant digit of the displayed results. The inherent ± 1 count error will result in a resolution of ±10-n Hz. Frequency multiplication is achieved using a phase-locked loop stage which provides a multiplication factor of 103. This method has the advantage of being simpler and less expensive compared to other methods using period-measuring techniques.

Method and machine for checking bank or postal cheques

Abstract: The invention relates to a method and a machine for checking the legality of issue of a bank or postal cheque with a view to allowing the payee to detect a stolen cheque The machine comprises a microprocessor ( mu P), means for acquiring the account number inscribed on the cheque (MG), means for conversion into binary ( mu P), logic calculation means (CAL) adapted to make the foregoing set of holder account numbers in a binary base correspond to the image set of the binary numbers with at most 14 bits, a decimal input system (CL) for insertion of a confidential four-number decimal code, means of conversion of the code into binary base (CV), means of temporary memory storage for the said code (RAM), logic means (COMP) for comparison of the result issued by the calculating means and of the memory-stored binary base code, and warning means AFF; SON; LA3; LA4 for interpreting the results of the comparison in a simple form

Accurate arithmetic results for decimal data on non-decimal computers

Abstract: Recently, techniques have been devised and implemented which permit the computation of smallest enclosing machine number interval for the exact results of a good number of highly composite operations. These exact results refer, however, to the data as they are represented in the computer. This note shows how the conversion of decimal data into non-decimal representations may be joined with the mathematical operation on the data into one high-accuracy algorithm. Such an algorithm is explicitly presented for the solution of systems of linear equations.

Informational device adapted to convert binary to decimal numerals

Abstract: A stack of sheets, each sheet from the next to lowermost upwardly corresponding to a successive binary place, the lowermost sheet carrying array of decimal numerals, a pivot connecting the sheets for relative rotation, and a window in each sheet above the lowermost configured to expose in one position of sheet movement the decimal corresponding to the binary place of the respective sheet and additional decimal numerals.

A new residue to decimal converter

Abstract: The Chinese Remainder Theorem, or CRT, is investigated in the context of its architecture. A novel architecture based on radix 2shardware is developed. By propedy managing a stack of system-wide carry bits, a CRT can be efficiently designed. The developed method is compared to more traditional techniques and is found to have a significantly reduced hardware budget.

Dual function decimal key

Abstract: The number of keys on a keyboard are reduced by employing the decimal point key as a control key when stroked the second time in the entry of a decimal number word. This eliminates the need for a key standard in the computer arts which is either designated as an "enter" key or as an "=" key depending upon the computer arithmetic process. It thereby becomes possible to use only twelve keys on a keyboard to control a modern computer with the order of 133 built-in programs or execution commands. This is done by providing in addition to ten decimal keys 0 to 9 and the decimal point key one additional control or execute key which initiates a two or more sequential key program step select mode in which any of the twelve keys are then stroked to designate a particular execution command. An accompanying graphic display of the various execution choices available makes the keyboard usable without necessity of frequent consultation of an instruction manual.

Electronic typewriter selectively responsive to set tabs and set decimal point tabs

Abstract: An electronic typewriter includes: a carriage mounting a printing unit; a control unit for controlling the movement of the carriage; a first setting unit for setting a print start position at a preset position, a second setting unit for setting a decimal point tab position so as to align decimal point positions while printing; and a decision unit for deciding whether the control unit is to control the carriage on the basis of the decimal point position set by the second setting unit. The carriage is stopped at the decimal tab position if it is necessary, while the carriage is not stopped at the decimal tab position if it is not necessary. Thus, the operator can perform the tab operations without paying attention to the decimal tab position. Alternatively, instead of the decimal tab position, such control may apply to the tab position.

Multiple accuracy floating point adding circuit

Abstract: PURPOSE:To obtain a multiple accuracy floating point adding circuit having high speed at an operating speed, flexibility of the circuit and possibility of expansion by connecting plural single accuracy floating point adder circuits in cascade. CONSTITUTION:Four single accuracy floating decimal fractions are operated in parallel while being synchronized with the same clock and each single accuracy performs non-normalizing addition or normalizing operation once per one clock. For example, the executing procedure of 4-time accuracy floating point addition of two 4-time accuracy floating decimal fractions A=A1+A2+A3+A4, B= B1+B2+B3+B4 is 12 steps and no overlap exists between A1-A4, B1-B4. The four single accuracy floating decimals Q1, Q2, Q3, Q4 being the final result of the addition 12-step are 4-time accuracy floating decimal fractions normalized without overlap. Although the result of addition Q1+Q2+Q3+Q4 is not coincident with the sum A+B of the 4-time accuracy floating fractions being accurate inputs and it contains an error at the 2 or 3 bit of the least significant digit and it causes no problem.

Computer-administered individualized psychological testing: a feasibility study

Abstract: The advent of microcomputers promises to open up a new era in psychometrics. In order to tap the full potential of the computer, it should do more than simply administer and score psychological tests, generate interpretations and graph the results. Psycho-metricians should tap the decision-making capacity of the computer, so that the most information can be generated from the fewest questions necessary accurately to assess, diagnose and treat the patient. This exploratory study explores the feasibility of converting the full-length Minnesota Multiphasic Personality Inventory (566 items) into a shorter form using a computer to individualize the number of items needed to reproduce a full-scale MMPI. 499 subjects from Kaiser Permanente (Southern California Region) who had taken the MMPI-566 in the paper and pencil format were used for the norming group, and 489 subjects from the same population were used for the comparison group. Multiple regression equations were produced for each step, and the computer generated a new equation for each item until criterion (matching two consecutive predictions, accurate to the first decimal place) was reached. The mean of the correlations comparing the predicted raw scores against the actual raw scores (scales across subjects) was r = 0-95, with a range of 0·88 to 0·98. The mean of the correlations comparing the predicted profiles (subjects across scales) was r=0·98 for the norming group and r=0·97 for the comparison group. The mean number of items needed for the comparison group was 187 (after adjusting for item overlap), and the profile correlation by subject for number of items needed was r=0·20. It was concluded that (1) psychological tests can be developed that will allow for individualized computer administration and (2) scores on these tests can accurately predict the scores on tests from which they were derived. Implications for use of computers in psychometrics are discussed.

Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction

Abstract: A bit sliced decimal adding/subtracting unit includes an 8-digit decimal adder/subtracter and an offset data generator. In the 8-digit decimal adder/subtracter, eight 1-digit decimal adder/subtracters are intercoupled so as to allow a carry to propagate from the lower order digit to the higher order digit. The offset data generator has first and second logical gates. The first logical gate detects whether or not an addition mode is specified by operation mode data. The second logical gate determines that a signal ZONE representing the format of the data to be operated represents a zone format, and that the addition mode is detected by said first logical gate. The output signal from the first logical gate is used for the first and second bits of the first 4-bit offset data. The output signal from the second logical gate is used for the 0th bit (MSB) and the third bit (LSB) of the first offset data. The output signal from the first logical gate is also used for the first and second bits of second 4-bit offset data. The 0th bit and the third bit of the second offset data are fixed at logical 0. The first offset data is supplied to the offset inputs of the adder/subtracters at the even digits (where the most significant digit is the 0th digit, and the least significant digit is the seventh digit) of the eight 1-digit decimal adder/subtracters. The second offset data is supplied to the offset inputs of the adder/subtracters at the odd number digits of the eight 1-digit decimal adder/subtracters.

Decimal operation processor

Abstract: PURPOSE:To execute operation with the minimum number of hardwares by providing the titled device with registers latching an operand consisting of a four- bit BCD code and a number to be operated respectively and registers latching a selector and its output, and reading out the contents of a ROM from these registers. CONSTITUTION:A bit string constituted of the outputs of the register 32 latching the operand expressed by a four-bit BCD code corresponding to one digit of data, the register 33 latching the operated number and the register 31 latching a carrying number and an initial value is connected to an address input of the ROM1. The ROM1 outputs four bits of the operated result in accordance with the input and four bits of a carried number by a selector 4. Consequently, the operation of decimal data consisting of the optional number of digits can be attained by the minimum number of hardwares without increasing the bit width of a data bus and the registers.

Transferring method of data displayed by bcd code

Abstract: PURPOSE:To reduce remarkably the number of signal lines by sending out a discriminating code, and thereafter, transferring successively a binary code of 4-bit for displaying the contents of decimal each digit of a data, in parallel at every decimal each digit. CONSTITUTION:With regard to a data of a control parameter, etc., for instance, in case when a decimal number of 6789 is transferred, first of all, a discriminating code for making an object to be controlled discriminate what the data is sent out together with a strobe signal. Subsequently, a binary code of six for displaying the contents of 1,000 digits is sent out together with a strobe signal. Thereafter, a binary code of seven for displaying the contents of 100 digits is sent out together with a strobe signal. In the same way, a binary code for displaying the contents of a digit of ten and a digit of one is transferred successively together with a strobe signal. A microprocessor of a controlled system OBJ selects a corresponding output port by discriminating code, also executes a series/parallel conversion to decimal each digit from a controlling circuit CONT, restores it to a decimal number, and outputs it to a selected output port.

A LISP System for Chemical Groups: Wigner — Eckart Coefficients for Arbitrary Permutation Groups

Abstract: Computer applications of group theory have almost invariably used numerical representations of the fundamental quantities of the group. For example, the combination laws in the crystallographic groups have been described as matrix multiplications on tables of coordinates [1]. These decimal values are approximate specifications of in principle exactly equivalent points. The finite mathematics realized in computers does not permit the numerical operations to represent faithfully the group theoretic operations.

Decimal arithmetic processor

Abstract: PURPOSE:To improve the numeric expression capability by about 1/2 digit in comparison with a conventional device to improve the efficiency of a memory area where decimal data is stored, by applying decimal data in a new data format having the complement expression where the most significant digit is a data digit used for numeric value as well as sign. CONSTITUTION:When subtraction is designated, signal '1' from a CPU is inputted to an FF55. Minuend and subtrahend data are loaded to registers R1 and R2 respectively. Subtrahend data is subtracted from fixed value '9916' by a subtractor 51, and the result is set to a register R3. Contents of registers R1 and R3 and the FF55 are added, and the result is loaded to registers R4 and R5. The exclusive or between contents of registers R1 and R3 is operated by a means 59 and is loaded to a register R6, and the exclusive OR between the addition result of contents of the register R5 and '6616' and contents of the register R6 is operated by the means 59, and the AND between this result and '11016' is operated by a means 60 to obtain an intermediate result Q1. The intermediate result Q1 is divided by '1016', and the result is multiplied by '616' to obtain an intermediate result Q2. The intermediate result Q2 and contents of the register R4 are added, and the addition result is loaded to a shift register SR and is sent to the CPU through a bus 43.

Normalizing circuit of binary-coded decimal number

Abstract: PURPOSE:To attain a high-speed operation of a normalizing circuit of binary- coded decimal number by shifting the input data after detecting ''1'' that is most approximate to the most significant bit of the input data CONSTITUTION:A preceding ''1'' detecting circuit 1 uses the data X of mantissa part as an input and detects ''1'' most approximate to the most significant bit MSB including this MSB and informs this detection information to an encoder 2 The encoder 2 converts the number of shifts into a code of binary display to perform normalization according to the received information A shifter 3 obtains the input of the data X and shifts the data X according to the shift information which is coded by the encoder 2 to produce the nomalization data Y This circuit ensures a normalizing action at a high speed

Method for comparing display key of decimal number

Abstract: PURPOSE:To obtain a decimal number key comparing method capable of comparison of decimal number keys successively from the leading byte similarly to binary numbers by displaying the code of the low-order bit of the least significant byte by the high-order bit of the most significant byte as a code, and converting a negative number into its complement to display it. CONSTITUTION:A key number to be compared and retrieved is inputted to a retrieving part 1, which retrieves a file 5 and takes out the corresponding address. The retrieving part 1 discriminates the code of the input key and that of the address to determine the size of the codes and then a comparing part 3 compares the code of the input key with the high-order bit. The comparing part 3 actuates a shifting part 4 in accordance with compared result and the retrieving part 1 retrieves the file 5 by shifting the retrieving position right or left in accordance with the compared size. Said process is repeated to retrieve the corresponding key.

Decimal arithmetic device

Abstract: PURPOSE:To attain a direct calculation of the input data of an unpack style through a decimal addition/subtraction circuit, by using a PG generating circuit which produces a carry transmission function and a carry production function from two binary code decimal data. CONSTITUTION:A decimal addition/subtraction circuit is provided with the 1st input circuit 4, the 2nd input circuit 5, a binary adder 6 and a decimal correction circuit 7. The circuit 4 adds 6 to each digit of the input data A and supplies then to the adder 6 if an addition is indicated from an addition/subtraction indicating circuit 80. In a subtraction mode the circuit 5 inverts an operand B and supplies it to the adder 6. A PG generating circuit 90 uses the outputs of circuits 4 and 5 to produce both a carry transmission function and a carry production function for each digit with an algorithm similar to a conventional one. A carry generating circuit 10 supplies a carry transmission function Pi and a carry production function Gi for each digit from the circuit 90 and produces the carry information Ci for each addition unit (digit unit).

Decimal multiplying circuit

Abstract: PURPOSE:To perform decimal multiplication processing speedily through a small number of steps by calculating some of partial multipliers of a multiplicand previously, and performing arithmetic among proper partial multipliers according to a multiplier and calculating multiples of the multiplicand. CONSTITUTION:A register 11 holds the multiplicand and its multiples which are twice, four times, and eight times. A register 2 holds the sum of partial products being calculated, and makes a shift in a next step. A register 3 holds the multiplier and also performs shifting operation associatively with the register 2. A selecting circuit 12 is controlled by a control circuit 13 to select a specific multiple in the register 11 and addition or subtraction according to the numeral of the lowest-order position of the register 3. The decimal arithmetic circuit 5 adds the specific multiple selected by the circuit 12 to the output of the register 2 to supply the sum of partial products to the register 2 and also performs multiple calculation and the addition or subtraction of the specific multiple. Thus, decimal multiplication is performed through a small number of steps.

Hard copying machine of two-dimensional video

Abstract: PURPOSE:To recognize the entire image qualitatively and to attain print display to each picture element by means of a concrete numeric value by converting a luminance data into a decimal number, deciding the color with a numeric value of the tens digit and printing out the numeric value of the units digit with the color. CONSTITUTION:The luminance data of each picture element stored in a picture memory 2 is converted into a decimal number by a numeric value processing section 3, the numeric value of the tens digit as a color code and the numeric value of the units digit is transmitted to a printer 4 as a character code. As a result, the qualitative recognition for the entire contrast of image is attained only at a glance and the luminance data to the picture element is discriminated.