Showing papers on "Distributed memory published in 1971"

The Organization and Use of Parallel Memories

Abstract: As computer CPUs get faster, primary memories tend to be organized in parallel banks. The fastest machines now being developed can fetch of the order of 100 words in parallel. Unless memory and compiler designers are careful, serious memory conflicts and resulting performance degradation may result. Some of the important questions of design and use of such memories are discussed.

Memory control in a multipurpose system utilizing a broadcast

Abstract: In a multiprocessing computer where a plurality of processors, each with its own buffer memory, share a main memory, a broadcast system provides each processor the capability to query each other processor to determine whether a modified (e.g. updated) version of the desired data is located in another processor''s buffer memory. The memory control unit simultaneously initiates a main memory read cycle and a broadcast signal in response to a request for data. If a modified version of the data is found to be in a buffer memory, it is transferred to the main memory by the control unit. The main memory read cycle is then changed to a write cycle so that the modified version replaces the original data. The modified data is then switched onto the memory data bus and transmitted to the requesting processor. Using this system, which only allows one buffer to contain a modified version of any data item, the requesting processor obtains the most current data in one main memory cycle in such a manner that it appears that the data is originating from main memory.

A Fault-Tolerant Information Processing Concept for Space Vehicles

Abstract: A distributed fault-tolerant information processing system is proposed, comprising a central multiprocessor, dedicated local processors, and multiplexed input–output buses connecting them together. The processors in the multiprocessor are duplicated for error detection, which is felt to be less expensive than using coded redundancy of comparable effectiveness. Error recovery is made possible by a triplicated scratchpad memory in each processor. The main multiprocessor memory uses replicated memory for error detection and correction. Local processors use any of three conventional redundancy techniques: voting, duplex pairs with backup, and duplex pairs in independent subsystems.

Data processing system having an improved fetch overlap feature

Abstract: An improvement in a fetch overlap feature for a data processing system results from providing multiple interfaces between the system data processor and the system memory. The memory is divided into a plurality of independent units each having its own interface. The data processor can retrieve more than one word from the memory system at the same time without incurring contention between memory access orders. The data processor is thereby enabled to begin to fetch its next instruction even if its current instruction orders the data processor to retrieve an operand.

C.ai: A Computing Environment for AI Research. Overview, PMS and Operating System Considerations

Abstract: : A computer for artificial intelligence research is examined. The design is based on a large, straightforward primary memory facility (about 8 million 74 bit words). Access to the memory is via at least 16 ports which are hardware protected; there is dynamic assignment of the memory to the ports. The maximum port bandwidth is 8,600 million bits/sec. Processors for languages (e. g., LISP) and specialized terminals (e.g., video input/output) can be reliably connected to the system during its operation. The approach is evolutionary in that high performance processors, such as the Standford AI Processor, can be connected to the memory structure, giving an overall power of at least 100 times a PDP-10 (and 200 to 300 times a PDP-10 for list processing languages) for 10 processors -- although 20 processors can be attached.