Showing papers on "Effective number of bits published in 1969"

Augmented digital-error-correcting decoder

Abstract: An error correcting decoder circuit for decoding redundantly coded received digital signals. Estimator bits are generated from selected bits of a received code word, and estimator reliability signals are generated in accordance with word-bit error probability signals derived from the received analog signal amplitudes associated with the same selected bits of the code word as are used for generating the estimator bits. The estimator reliability signals are used as a basis for weighting the bipolar estimator bit voltages, by increasing or decreasing their absolute values, whereby the more reliable estimator bits are given greater weights at the input of a threshold decision circuit. The threshold decision circuit generates an output bit in accordance with the arithmetic sum of the weighted estimator bit voltages, except that it substitutes the appropriate received bit in place of the unreliable threshold decision that arises in the event that the sum is small in magnitude. Control circuitry is provided for causing repetitive shifting of the word bits in a first shift register and of word-bit error probability signals in a second shift register, for performing step-by-step decoding of a received word with the aid of the received signal reliability indications. The invention thus provides a means of augmenting the digital error correction capability of decoders through the use of auxiliary outputs from the receiver which indicate the received signal quality.

Error-detecting system for data-processing circuitry

Abstract: This invention is directed to error detection circuitry for combination with data-processing systems The information which comprises the message transmission is transmitted in binary fashion in channels each of a selected number of data bits, and through the addition of two check bits it is possible to detect both single and double parity errors of the asymmetric-type