Showing papers on "Electronic circuit simulation published in 1982"

SPICE Modeling for Small Geometry MOSFET Circuits

Abstract: VLSI circuit simulation requires computationally efficient MOSFET models. In this paper, VLSI circuit simulator models for the active device and some important passive devices are described. A quasi-physical short channel MOSFET current model is derived. This current model contains both above-threshold and subthreshold components. The values of the model parameter are extracted automatically from measured I-V data. The reduction in process information in this representation is shown to be tolerable using a proper quantization of the geometry and device type space. Narrow width effect is also included. A charge conserving MOSFET capacitor model is also given. The importance of the parasitic devices on VLSI circuit is shown and a model for the fringing capacitance due to finite gate thickness is introduced. A "process box" based on the statistical variation of parameters is extracted from a completely automated device characterization system. Experimental results indicate that the width and length are independent random variables. This statistical information allows the circuit response to be simulated across the process window.

Synchronous Path Analysis in MOS Circuit Simulator

Abstract: For verifying the timing performance of synchronous MOS circuits a path analysis facility has been developed in the MOTIS (MOS Timing Simulator) system. This path analysis traces the clock signals to the latches in the circuit, computes the clock skews and then performs a path search analysis between all latches. For the paths between clocked latches, the timing constraints are determined using the clock skews and the operating frequency. The paths that do not satisfy these constraints are identified as problem paths. Such an analysis does not require a prior generation of circuit stimuli that are necessary for simulation. In terms of complexity also, it is simpler than simulation.

RELAX: A New Circuit Simulator for Large Scale MOS Integrated Circuits

Abstract: Algorithms and techniques used in RELAX are described. RELAX is a time domain MOS digital circuit simulator based on a new analysis method called Waveform Relaxation Method [1] which exploits decomposition techniques. Preliminary comparisons between RELAX and the standard circuit simulator SPICE2 have shown that RELAX is a fast and reliable circuit simulator.

Circuit simulation on vector processors

Abstract: Vector computers have an increased potential for fast, accurate simulation at the transistor level of circuits. Design considerations for a new circuit simulator are developed based on the specifics of the vector computer architecture and of LSI circuits. The performance of the new LSI simulator, CLASSIE, is evaluated on a Cray-1 vector-computer for several circuits with from a few hundred to over one thousand semiconductor devices. Comments are given concerning the performance limits and relative hardware dependence. 6 references.

Relax: A new circuit for large scale MOS integrated circuits

Abstract: Algorithms and techniques used in RELAX are described. RELAX is a time domain MOS digital circuit simulator based on a new analysis method called Waveform Relaxation Method [1] which exploits decomposition techniques. Preliminary comparisons between RELAX and the standard circuit simulator SPICE2 have shown that RELAX is a fast and reliable circuit simulator.

Exploitation of Hierarchy in Analyses of Integrated Circuit Artwork

Abstract: The artwork of integrated circuit designs is usually available in the form of hierarchical specification, in which each cell is made up of geometric primitives and references to other cells Such a representation captures structure and repetition in the layout As the realizable device count of integrated circuits increases with every passing year there is an increasing trend towards structured design approaches that result in even greater degrees of regularity and hierarchy Yet the typical approach to design verification requires fully instantiating the hierarchical representation thereby removing all structure from it Consequently much time is spent repeating the analyses of identical cells This paper presents a general approach to exploiting hierarchy and repetition in the analysis of integrated circuit designs, and includes details of a circuit extraction algorithm that uses this approach The implementation and performance of such a system is also described

Lsi circuit simulation on vector computers (spice2, classie)

Abstract: The simulation of Large-Scale-Integrated (LSI) circuits requires very long run times on conventional circuit analysis programs such as SPICE2. A new simulator for LSI circuits, CLASSIE, has been developed which is more efficient and preserves the same accuracy. Two basic factors of present technology are considered in the design of the new LSI circuit simulator. First, LSI circuits are usually a collection of a limited number of structurally identical functional blocks such as logic gates, operational amplifiers, etc. The second is the availability of vector computers which provide an ideal architecture for fast computations on repetitive structures. SPICE2 operates on an entire circuit matrix which is processed at the individual electrical element level. The analysis in the new program takes into consideration the structure of the LSI circuit. The identical functional blocks are grouped together and the simulation is performed at two levels. The above design considerations speed up the simulation of an LSI circuit performed by CLASSIE considerably compared to SPICE2. For the analysis of a large circuit, CLASSIE on a vector computer rates in simulation speed between SPICE2 and a timing simulator. For various test circuits containing from a few hundred to a few thousand semiconductor devices, CLASSIE simulation runs on a CRAY-1 indicate that the speedup compared to SPICE2 increases with circuit size. The solution techniques implemented in the new simulator make the execution time grow linearly with increasing circuit complexity in comparison to an exponential growth in a conventional circuit simulator. Vectorized device-model evaluation and a machine-code solver using both vector and scalar operations bring about the increased performance. A program such as CLASSIE creates a framework for hierarchical circuit simulation. The decoupling of the analysis at the subcircuit (cell) level allows the implementation of direct solution algorithms, as in CLASSIE, as well as indirect (relaxation-type) solution algorithms in further programs. Further modifications can be made for optimal performance on various computer architectures (single-instruction single-data stream, single-instruction multiple-data stream, and multiple-instruction multiple data stream).

Circuit Analysis and Simulation Programs -An Overview-

Abstract: The paper is intended to be a tutorial-like description of the development of electrical circuit analysis programs used for analyzing digital and analog circuits. The anatomy of circuit simulator programs, analysis formulation techniques, and solution procedures will be addressed. A few of the features, capabilities, and limitations of several of the more widely used current programs will also be covered.

WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits

Abstract: Recent advances in integrated circuit technology have involved process development, device, and circuit optimization under scaled design rules. It is advantageous to be able to simulate the overall circuit performance under different conditions. A simulator which performs this task at the logic gate level becomes important. This paper describes such a simulator for digital bipolar integrated circuit families: WATPAC. WATPAC uses the process simulator SUPREM, the device simulator BIPOLE, and the circuit simulator WATAND. The input parameters to WATPAC are entered interactively. These consist of fabrication process parameters, layout design rules, a specification of the logic family, and a WATPAC predefined logic function. The WATPAC output consists of overall circuit performance data for the simulated function block. The output of WATPAC also includes the intermediate outputs of the process simulator, device simulator, and the circuit simulator.