Showing papers on "Field-programmable gate array published in 1970"

A Compact 32-bit Architecture for an AES System

Abstract: This paper describes a compact 32-bit architecture developed for the Rijndael ciphering/deciphering system. The implementation is complied with NIST Advanced Encryption Standard (AES). The design processes any 128-bit block data with 128-bit key. For the compact hardware, the field inversion circuit and the key scheduling circuits are shared by both the encryption and decryption process. The on-the-fly KeyScheduling implementation offers fast processing speed but with core size trade-off. According to the evaluation made on the targeted FPGA, the design can offer the throughput of 768 mbps at 264 MHz clock speed.

Using an FPGA implementation of the multicycle mips machine to teach reconfigurable computing in the new ehea

Abstract: Reconfigurable Computing is a very important discipline nowadays. Furthermore, with the new hardware description languages like Handel-C the change to hardware programming is easier for the computer engineers. In this work, we present a proposal of course