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Showing papers on "Ground bounce published in 1979"


Patent
Sheng T. Hsu1
10 Aug 1979
TL;DR: In this article, a nonvolatile memory structure of the floating gate type is described, where current carriers are injected onto the floating gated from the control gate from the substrate.
Abstract: A non-volatile memory structure of the floating gate type is described wherein current carriers are injected onto the floating gate from the control gate as distinguished from the prior art which injects current carriers into the floating gate from the substrate. This invention teaches that by tailoring the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the substrate different field intensities are created in the region between the floating gate and the control gate and in the region between the substrate and the floating gate. When the field intensity across the capacitor formed between the control gate and the floating gate is greater than the field intensity across the capacitor formed between the floating gate and the substrate, current carriers will be injected onto the floating gate from the control gate.

19 citations


Journal ArticleDOI
Nakamura1
TL;DR: The problem of synthesizing logical networks, with negative gates only, is important for the design of MOS LSI.
Abstract: A negative gate is a gate which can realize an arbitrary negative function. The problem of synthesizing logical networks, with negative gates only, is important for the design of MOS LSI.

10 citations


Patent
28 Sep 1979
TL;DR: In this paper, a memory circuit suitable for large scale integration is described, which consists of a plurality of memory cells each including a gate transistor having a gate coupled to one of word lines and a drain coupled to digit lines and capacitor means coupled between a source of the gate transistor and a potential source.
Abstract: A memory circuit suitable for large scale integration is disclosed. The memory circuit comprises a plurality of memory cells each including a gate transistor having a gate coupled to one of word lines and a drain coupled to one of digit lines and capacitor means coupled between a source of the gate transistor and a potential source, wherein the threshold voltage of the gate transistors is made smaller than that of logic transistors employed in peripheral circuits.

5 citations