Showing papers on "Hardware register published in 1983"

Apparatus for controlling the background and foreground colors displayed by raster graphic system

Abstract: Apparatus for controlling the colors displayed by a raster graphic system. Information stored at each addressable location of a RAM includes a set of behavior bits and a set of control bits. These bits are read out of memory during each memory read cycle. The control bits are stored in a shift register and the behavior bits are applied to an escape code detector and may be stored in a foreground or a background behavior register if enabled by the detector. One control bit is shifted out of the shift register each pixel clock pulse. This control bit determines the register from which the behavior bits are selected to form a color index. The index includes behavior bits from the selected register and the control bit for the pixel being scanned. This index is applied to a color look-up memory which produces color control signals which are applied to D/A converters, the outputs of which control the color and intensity of each pixel of the raster. A certain set of behavior bits, an escape code, causes the detector to inhibit both behavior registers from storing the escape code and enables the background behavior register to store the next set of behavior bits read out of memory. Thereafter the escape code detector enables the foreground register to store behavior bits produced from memory during each memory read cycle until the next escape code is detected.

The Piecewise Data Flow architecture control flow and register management

Abstract: This paper presents the hardware register management and instruction block control flow sequencing provided by the PDF block processing section of the Piecewise Data Flow machine, a proposed high performance computer architecture. Combined, these capabilities provide the maximum allowed execution overlap of instruction blocks with minimum hardware contention and high hardware utilization.

Hardware Design of a Digital Synthesizer

Abstract: The synthesizer discussed here was designed as a means of generating time-variable spectra by evaluation of algebraic time-dependent functions. In addition to additive synthesis algorithms, many algebraic functions are known that efficiently yield such spectra. The functions themselves are often compact, and they are inherently hardware independent; accordingly, the design strives to reflect these attributes in a straightforward architecture that emphasizes hardware transparency.

Status information transfer

Abstract: Multi subchannel adapter for a programmed control unit arranged to be operated in facilitating I/O operations between one or more I/O devices and a CPU through a channel, including a local store (17) which comprises a hardware register dedicated to store device status (RNB) and the associated address (RNA) in connection with test I/O commands. Thus, on receiving a status request the adapter responds immediately with a response indicating that the information is not immediately available, for example, a busy response. The adapter initiates an interrupt to the programmed control unit to obtain the requested status information, which is then stored in dedicated hardware register (RNA, RNB) of the local store (17). On the next subsequent test I/O command to the same address, the adapter responds with the status as read from the dedicated hardware register (RNB).

Piecewise data flow architecture control flow and register management

Abstract: The hardware register management and instruction block control flow sequencing provided by the PDF block processing section of the Piecewise Data Flow machine, a proposed high performance computer architecture, is presented. Combined, these capabilities provide the maximum allowed execution overlap of instruction blocks with minimum hardware contention and high hardware utilization.