Showing papers on "Logarithmic number system published in 1994"

Interleaved memory function interpolators with application to an accurate LNS arithmetic unit

Abstract: This paper describes a new method for polynomial interpolation in hardware, with advantages demonstrated by its application to an accurate logarithmic number system (LNS) arithmetic unit. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy can be shown to always use fewer words of memory than an optimized polynomial with stored polynomial coefficients. Interleaved memory function interpolators are then applied to the specific goal of an accurate logarithmic number system arithmetic unit. Many accuracy requirements for the LNS arithmetic unit are possible. Although a round to nearest would be desirable, it cannot be easily achieved. The goal suggested is to insure that the worst case LNS relative error is smaller than the worst case floating point (FP) relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second order polynomial interpolator including approximately 91K bits of ROM. This arithmetic unit has better accuracy and less complexity than previous LNS units. >

The chip design of a 32-b logarithmic number system

Abstract: To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log/sub 2/(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 2/sup 0.x/ function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor. >

Apparatus for calculating the square root of the sum of two squares

Abstract: A first digital signal of a serial form is processed into a second digital signal of a serial form. The second digital signal represents an absolute value of a value represented by the first digital signal. A third digital signal of a serial form is processed into a fourth digital signal of a serial form. The fourth digital signal represents an absolute value of a value represented by the third digital signal. The values represented by the first and third digital signals are compared to generate a comparison-result digital signal representing a result of the comparison. A calculation-result digital signal of a serial form is generated in response to the second digital signal, the fourth digital signal, and the comparison-result digital signal. The calculation-result digital signal represents a value which is approximate to a square root of a sum of a square of the value represented by the first digital signal and a square of the value represented by the third digital signal.

Novel floating-point A/D- and D/A-conversion methods

Abstract: Floating-point arithmetic offers several benefits in digital signal processing. Floating-point A/D- and D/A-converters are needed in the realization of true floating-point signal processing systems. Novel, simple floating-point A/D- and D/A-conversion methods, based on the close resemblance of floating-point and logarithmic number representations, are introduced in this paper. These methods are easy to tailor to different specifications, and they offer a simple trade-off between dynamic range and accuracy. >

An improved method of scaling for real-time signal processing applications

Abstract: Implementing digital signal processing algorithms using fixed-point arithmetic is a difficult task, involving trade-offs to balance the efficiency and noise performance of a given realization. One of the most important components of such design is to minimize the noise generated by quantization and over flow effects. This is generally accomplished by the scaling of signals and coefficients in the fixed-point realization based upon knowledge of signal features and statistics. This paper presents a new method for structuring this design task. It uses a model based on scaled-fractional numbers to simplify both the concepts required to realize fixed-point arithmetic versions of algorithms, as well as the real effort required for such implementations. This model has been implemented as a data type in a high level computer language to allow direct implementation of fixed-point arithmetic versions of algorithms. >

Method and apparatus for converting an analog signal to a digital floating-point number and a digital floating-pont number to an analog signal

Abstract: A method for converting an analog signal to a digital floating-point number and a digital floating-point number to an analog signal. According to the invention, A/D conversion is performed by forming a logarithmed signal (log|x| ) from an analog signal (x) by a logarithmic function having an arbitrary base, converting the resultant signal to digital form (z) by fixed-point A/D conversion, separating the exponent (c) of the floating-point number from the digitized sample value and calculating the mantissa (m q ) of the floating-point number from the fractional part (f) by a base 2 exponential function. Correspondingly, D/A conversion is performed by converting the mantissa (m q ) of the floating-point number by a logarithmic function having an arbitrary base to the exponent of the base, adding the converted mantissa and exponent, converting the digital number (z 2 ) obtained by conversion to an analog signal by fixed-point D/A conversion, and forming from the converted signal a signal that represents its base 2 exponent.

Floating point addition errors and their effect on the roundoff noise in digital signal processing

Abstract: An improved adder model is derived which takes into account correlations between signal and error For different adder strategies is shown the influence of the improved adder model on the estimated of the resulting SNR >

Required coefficient word length in floating-point and logarithmic digital filters

Abstract: The effects of coefficient quantization to the response of a digital filter are studied. Easy-to-use expressions for the required coefficient word length, with which the filter response deviations are within specified bounds, are derived for filters realized with floating-point or logarithmic arithmetic. The required coefficient word lengths of floating-point and fixed-point realizations of filters are compared with simulations. >

A new WDF three-port adaptor suitable for floating-point arithmetic and/or DSP implementations

Abstract: A new decomposed version of three-port adaptors for wave digital filters (WDFs) is proposed, which is especially suitable for floating-point arithmetic and for implementation on digital signal processors (DSPs). By using the proposed three-port adaptor, the concept of modified wave digital filters (MWDFs) is appropriately extended to WDFs involving any n-port adaptors (n is integer). The resulting MWDFs preserve all the important properties of WDFs, in particular, those relating to stability. >

Floating point quasi maximum accuracy arithmetics for digital signal processing

Abstract: Floating-point arithmetics for digital signal processing are considered. In order to minimize rounding noise, arithmetic operations should be computed possibly exactly. For that reason, maximum accuracy arithmetics are investigated. There are generally two ways to realize such arithmetics: a hardware solution and/or a software solution. The former uses standard floating-point arithmetics but is practically unrealizable because of the need of an extremely long accumulator. For the latter, new algorithms are developed. In order to realize signal processing tasks in real time, a compromise between computation time and accuracy must be found. This leads to the so called quasi-maximum accuracy algorithms which are investigated in this paper. >