Showing papers on "Multistage interconnection networks published in 2022"
3 citations
TL;DR: In this paper, new 3×3, 4×2, and 4×4 switching element (SE) structures are introduced which can be employed in various existing MINs to provide enhanced reliability at much reduced cost.
Abstract: Reliable and cost effective multistage interconnection networks (MINs) are the backbone of efficient distributed computing in supercomputer systems. In this paper new 3×3, 4×2, and 4×4 switching element (SE) structures are introduced which can be employed in various existing MINs to provide enhanced reliability at much reduced cost. The reliability function of proposed as well as the existing SEs have been formulated on basis of which their reliability values have been computed. The computed reliability values of all SEs (existing and proposed ones) have been compared and analyzed. The achieved results clearly depicts that the proposed SEs possess higher reliability and can replace the existing SEs of similar size without changing the existing design of MIN to improve reliability.
1 citations
03 Oct 2022
TL;DR: In this article , the analysis and calculation of insertion loss in multistage next generation photonic switches is presented for the first time, based on using the so-called connection diameter of the photonic switch for evaluation of loss.
Abstract: The analysis and calculation of insertion loss in multistage next generation photonic switches is presented in this paper for the first time. The theory is based on using the so-called connection diameter of the photonic switch for evaluation of loss. Furthermore, the expression for calculating the diameter of Close scheme has been obtain for the first time. The comparison of insertion losses in multistage photonic switches such as Close, Banyan, dual schemes and crossbar switch is presented. The evaluation of crosstalk in the photonic switches on example of dual switches based on physical principles of their functioning is considered.
23 Sep 2022
TL;DR: The 3-disjoint path partially chained multistage interconnection network (3-DP PCMIN) as mentioned in this paper is a modified version of the GIN that offers three disjoint paths between any source-destination (S-D) node pair in order to accommodate two switch/link failures.
Abstract: The 3-disjoint path partially chained multistage interconnection network (3-DP PCMIN) is a new multistage interconnection network that we present in this paper. It is a modified version of the GIN that offers three disjoint paths between any source-destination (S-D) node pair in order to accommodate two switch/link failures. It has lower hardware cost than GIN, 3DGIN and enhanced IADM. Here the compact expression for 2-terminal reliability of proposed design is also calculated using hybrid MVI algorithm. To show the advantage features of proposed design layout (3-DP PCMIN) we also make a comparison between 3-DCGIN, enhanced IADM, 3 DGIN and proposed design layout of 3-disjoint path partly chained MIN.
TL;DR: In this article , the authors proposed a peer k-ary n-tree or peer fat-tree network that takes the factors of path diversity, hardware cost, and packet latency into consideration.
Abstract: Clos- or fat-tree-based interconnection networks are widely used in data center and supercomputer designs. Both Clos and fat-tree are non-blocking multistage switch networks. The non-blocking property improves path diversity but meanwhile increases both hardware cost and packet latency. Some applications may not require non-blocking routing but prefer low packet latency. To cope with it, this paper proposes a peer k-ary n-tree or peer fat-tree network that takes the factors of path diversity, hardware cost, and packet latency into consideration. A peer k-ary n-tree network connects compute nodes with about half as many switches and links compared to Clos and fat-tree networks. It has two groups of compute nodes and provides short routing paths between the nodes in distinct groups and non-blocking routing between the nodes in the same group. We describe the peer k-ary n-tree network structure, investigate the topological properties, give a minimal per-hop deterministic routing algorithm, and evaluate the fault tolerance and packet latency of the peer k-ary n-tree network and compare the performance to that of Clos and fat-tree networks.