Showing papers on "Paging published in 1983"

Carrying case for portable electronic paging devices

Abstract: A carrying case for portable electronic paging devices has a partitioned receptacle assembly with a first receptacle to receive the paging device and a second receptacle to positively receive and engage the device's mounting clip. A releasable strap allows the receptacle assembly to be tripped or pivoted away from the wearer while being worn by the wearer to enable the paging device's controls or indicators to be generated or read.

Selective call paging and priority signalling system.

Abstract: A general purpose data control and information system (30-64) particularly well adapted for multiple unit (60-64) radio communications providing reliable enhancement to normal voice systems. The system provides addressing capability (Fig. 2, bits 0-15) along with data transfer (Fig. 3) and utilizes handshake and retransmission protocol to enhance flexibility and reliability. The system utilizes fixed length signalling packets, (Fig. 2), with error correction encoding, to permit data transfer, transmitter identification and control and status monitoring.

RESEARCH NOTE A Comparison of Paging and Scrolling for Changing Screen Contents by Inexperienced Users

Abstract: Paging and scrolling were compared as to their relative suitability for determining which part of a body of information is to be displayed on a screen. Unpracticed subjects performed three different tasks (word reading, line searching, sorting) with both modes of operation. The subjects also rated the suitability of the two modes of operation for each task. Paging was preferred by inexperienced users and it resulted in better performance on the sorting task.

Segmented one and two level paging address translation system

Abstract: An address translation system is provided which has a real storage, a virtual storage having a "V═R" segment (first segment), second segments to be subjected to two-level paging, and page table segments (third segments) to be used as a page table corresponding to the second segments, a segment table, a first page table which corresponds to the second segments, a second page table which corresponds to the page table segments, and a memory control unit having a virtual address register and a microprocessor for translating the virtual address in the virtual address register into a real address. By means of microprogram control, the microprocessor has a first address translation function for obtaining a real address from the page number and the displacement data of the virtual address if the segment number of the virtual address represents the first segment, a segment table referring function for referring to the segment table based on the segment number if the segment number does not represent the first segment, and a second address translation function for referring to the second page table based on the reference result from the segment table and the several most significant bits of the page number, for referring to the first page table based on the reference result of the second page table and on the remaining bits of the page number, and for obtaining the real address from the reference result of the first page table and the displacement data.

Display pager having memory overflow indication and concurrent message display functions

Abstract: A radio paging receiver for receiving a carrier wave modulated paging signal which includes a preamble, an address code and a message, is composed of at least a receiver section, a waveform shaping circuit, a memory section, a control section, a speaker with driving sectionto sound an alert signal and a display section. The memory section stores a predetermined number of received messages, which are counted as they are received by a counter in the control section. The display section under the control of the control section, produces a three part display, the first part being an indication of the age of the displayed message relative to the other messages stored in memory, the second part the call type, when a dual call service is implemented, and the last part one of the messages stored in memory. If a message is being displayed as a new message is received, the previous message continues to be displayed, while the new message is stored in memory if memory space is available. In addition, the receiver operates to change the first part of the display to inform the subscriber that a new message has been received.

Two-Level Replacement Decisions in Paging Stores

Abstract: One of the primary motivations for implementing virtual memory is its ability to automatically manage a hierarchy of storage systems with different characteristics. The composite system behaves as if it were a single-level system having the more desirable characteristics of each of its constituent levels. In this paper we extend the virtual memory concept to within the top level of a two-level hierarchy. Here, the top level is thought of as containing two additional levels within it. This hierarchy is not a physical one, but rather an artificial one arising from the employment of two different replacement algorithms. Given two replacement algorithms, one of which has good performance but high implementation cost and the other poor performance but low implementation cost, we propose and analyze schemes that result in an overall algorithm having the performance characteristics of the former and the cost characteristics of the latter. We discuss the suitability of such schemes in the management of storage hierarchies that lack page reference bits.

Digital paging system having bit rate switching means and digital paging receiver therefor

Abstract: A paging system in which an address code is transmitted at a lower transmission rate than message code and a discrimination code defines the boundary between the address and the message. The receiver includes a low pass filter with a cut-off frequency switchable between the reception rate for the address and the reception rate for the message in response to the discrimination code.

Apparatus and method for an operating system supervisor in a data processing system

Abstract: Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserve memory area associated with the currently active operating system is then addressed and register contents of a central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory and, data establishing the decor of the operating system being activated are entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun. The physical memory locations are determined by a real address through use of a paging mechanism permitting storage of portions of the operating systems in non-contiguous groups of locations while isolating the memory available to each operating system.

Radio paging receiver having stored message protection means

Abstract: A radio paging receiver is provided in which messages are continuously written into a first memory for subsequent display. A second memory is used to selectively prevent the erasure of messages written into the first memory when the first memory capacity has been exceeded.

Digital radio paging receiver

Abstract: The digital radio paging receiver comprises a first memory circuit for storing a first address codeword assigned to said receiver and comprised of a BCH code and a second memory circuit for storing a plurality of codewords, each comprising a BCH code whose information contents differ from said first address codeword only in a small number of specific bits. A code generator performs exclusive OR operation in a time series between the contents of said second memory circuit and of said first memory circuits, respectively, and provides as its output second address codewords corresponding to said first address codeword. A comparator time-serially compares a selective calling signal with said first and second address codewords to provide responsive to the results of comparison an identity signal representing the identity of said calling signal with said address codewords. This digital radio paging receiver is capable of detecting multi-address codewords with a reduced PROM capacity and a reduced number of shift registers. Furthermore, it can detect multi-address codewords and can be made more compact by reducing the number of socket leads for the cord plug.

Paging on an object-oriented personal computer

Abstract: @; programming environment are both to decrease the average page fault rate and to minimize the pauses caused by clusters of page faults. We have applied program restructuring techniques to the Smalltalk-80 object memory in order to improve the locality of reference. The analysis in this paper considers the clustering of page faults over time and distinguishes between steady-state behavior and phase transitions. We compare the effectiveness of different restructuring strategies in reducing the amount of main memory needed to obtain desired levels of performance.

Input/output paging mechanism in a data processor

Abstract: In a data processor performing an input and output paging function, a main memory (MMU) and an input and output processor (IOP) connected to the MMU through a bus are provided. The MMU stores a list-service page table for mapping a logical space in which channel command entries are located, and a data service page table for mapping the data transfer areas specified by channel command entries, pointers for the respective page tables, and flags for the designation of a physical or logical address. The IOP reads the pointers from the MMU, refers to the respective page tables, determines whether the specified address is physical or logical, and translates it into an effective address.

Implementing streams on a data flow computer system with paged memory

Abstract: In several data flow architectures, “streams” are proposed as special data structures able to improve parallel execution in functional programs by providing a pipelining effect between different program parts. This paper describes how streams are implemented on a data flow computer system based on a paged memory. This memory holds both the data flow programs and data structures such as streams. Streams are stored in the memory as a linked list of pages while pointers to the streams are flowing as data tokens. A reference count is used to prevent for excessive copying of data and to control the allocation and recovery of pages. Input/output is treated as a special application of streams.

Paging universal remote control system

Abstract: A paging station remote control system capable of providing analog or binary modulation modes is described. Control of the paging base station is effected through a signalling scheme comprising a combination of tones and timed pauses generated in response to control signals supplied either manually or by a paging terminal. The paging system is capable of transitions between binary and analog modulation modes without first dekeying the paging transmitter.

Individual simulcast station control system

Abstract: A simulcast paging transmitter remote control system capable of individual station control is described. The remote paging transmitter control system comprises an encoder and decoder which interface with a paging terminal and transmitter respectively. The system encoder and decoder communicate through a specifically formatted signalling scheme which is configured to provide station deactivation information as well as conventional paging information.

Individual simulcast transmitter remote control system encoder

Abstract: A paging simulcast station remote control system encoder is described. The paging system encoder generates signals in accordance with a predetermined signalling scheme comprising a series of tones and timed pauses and generated in response to control signals supplied either manually and or by a paging terminal. The paging system encoder provides control signals which instruct a paging transmitter to transmit a subsequent paging signal or to inhibit transmission until instructed to do otherwise. The paging encoder can generate signals to individually control as many as 30 individual simulcast transmission remote stations through an existing paging RF link.

Computer system with multiple operating systems

Abstract: A supervisor for data processing system capable of utilizing a plurality of operating systems includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserved memory area associated with the currently active operating system is then addressed and the register contents of the central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory, and data establishing the decor of the operating system being activated all to be entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun. The physical memory locations are determined by a real address through use of a paging mechanism permitting storage of portions of the operating systems in non-contiguous groups of locations while isolating the memory available to each operating system.

Vehicle message terminal

Abstract: A vehicle message terminal comprising a car radio receiver incorporating separate receiving circuits for paging messages and public entertainment broadcasts. The receiver has a common antenna input 11 for both circuits and a front panel 12 incorporating conventional radio tuning scales 13 and light emitting diode visual display 14 for paging messages. The paging receiver is powered from the vehicle battery via the ignition switch.

Data processing system

Abstract: PURPOSE:To improve the processing speed, by specifying an address at one end of an address section and preparing a virtual storage data set corresponding to the address section of a file at the state relocated in advance. CONSTITUTION:A program A on a file is registrated as a page file at the state extended and relocated in advance. In this case, the storage condition to the page file is confirmed to calculate a relocation address ad2 from an address ad1. A file Ar of the virtual storage is assigned as a page data of a virtual address section 21 relocated in a virtual storage address space 2. The address should be determined definitely. To determine the reference point in advance, an address 22 at one end of a virtual address section 21 is specified and the 1st address for relocation is fixed.

Radio paging receiver operable on a word-scrolling basis

Abstract: A radio paging receiver comprises a linear array of display elements, a memory having a plurality of storage locations for storing a received message code therein, and a microprocessor-based decoder. The microprocessor-based decoder is responsive to a received preamble code for detecting a match between an address code and a user's own code to store a message codeword into the memory in response to the detection of the match. A first sequence of characters is read from predetermined storage locations of the memory and fed to the display elements. In succession, a blank which immediately follows the first sequence is detected to read a second sequence of characters from the positions immediately following the detected blank and displayed by clearing the characters of the first sequence.

Individual simulcast station control decoder

Abstract: A paging simulcast station remote control system decoder. The paging system decoder responds to signals generated in accordance with a predetermined signalling scheme comprising a series of tones and timed pauses. The decoder is also responsive to user programmable switches which provide station function tone and sector information. The paging system decoder then selectively deactivates a paging simulcast transmitter in response to signals received through a conventional paging communication link.

Memory managing system

Abstract: PURPOSE:To improve the space efficiency of a main storage and reduce the load of swapping, by linking discontinuous areas for each task to acquire the partition on a physical memory in the operation area management of tasks on a memory. CONSTITUTION:Each task 8 has a partition managing part 9, and the presence or the absence of respective segments constituting the partition of the task 8, the update or transfer stage of contents of them, and storage positions of them are managed on a physical memory 2 and a swap file 3 by the table. A swap controlling part 10 manages the area acquisition of the physical memory required for the execution of the task 8. Therefore, the swap controlling part 10 refers to partition information of each task in the partition managing part 9 to control swap-in or swap-out of proper segments between the physical memory 2 and the swap file 3. The partition managing part 9 ranks states of segments to make it possible to select an optimum swap object segment.

The memory usage of a LISP system: the Belady life-time function

Abstract: In this paper we will describe the memory management of a LISP interpreter, implemented in FORTRAN. The memory is used to store both LISP programs and LISP data structures. The dynamic use of this memory was examined during the execution of a large LISP program. The usage of this memory seen as a paged memory was analysed in terms of the Belady Life-Time Function. The results of this analysis is presented.

Memory paging address conversion system

Abstract: PURPOSE:To attain conversion efficiency, by providing access page numbers at previous time and this time in memory paging conversion, omitting the conversion in coincidence, and guaranteeing the conversion time through the insertion of a wait cycle in discidence CONSTITUTION:A page address S2 of a logical memory address signal S1 outputted from a CPU is given to a page number latch circuit 2 and a comparator 3 When the memory access is started, the comparator 3 compares the page number at previous time latched in the circuit 2 with a new page number this time at the page address S2 When the both are coincident, the conversion is omitted through the accessing to the same page When discident, a wait cycle is inserted to a memory access cycle and converted into a physical address S7 with a memory paging table 1 Thus, the efficient conversion can be done with an inexpensive and low speed memory element

Detecting system for rewriting of instruction word

Abstract: PURPOSE:To ensure the accurate detection for the rewriting of an instruction word with a simple constitution for an information processor which applying both an advance control system and a paging system, by detecting the rewriting of the instruction of a prefetched instruction group from the result of an inspection. CONSTITUTION:When a prefetched instruction group is stored within a page, a page address 203 of a store physical address coincides with a fetched page address. Then it is understood that an address 204 within a page of the store physical address is included between a head address 209 and an end address 210. Thus the rewriting inspection signal 221 is delivered at the producing point of the detecting timing 218. In case the prefetched instruction group covers plural pages, the coincidence is detected between the address 203 and a page address 207 of the 1st page. When it is understood that the address 204 is larger than the address 209, the signal 221 is delivered. The signal is also delivered when the address 203 coincides with an address 206 and it is understood that the address 204 is smaller than the address 210.