Showing papers on "Parallel algorithm published in 1977"

Parallelism, Slides, Schemas, and Frames

Abstract: In BT (Brain Theory), we study nets of simultaneously active neurons, and of interacting brain regions. In AI (Artificial Intelligence), we must structure programs for a serial computer. However, the development of a serial algorithm for a function does not preclude the existence of a more efficient parallel algorithm. For example, when adding two numbers, the propagation of the carry bit seems to force seriality. However, a look-ahead adder (see Hill and Peterson (1973) for a textbook treatment) can be built which uses parallelism based on ‘carry look-ahead’ to reduce addition time from the order of n (the length of the numbers) to the order of log n which, in fact, is the best possible (cf. Winograd’s (1965)). Our task here is to examine the ways in which behavior is best expressed in structure, and consider the extent to which we can expect parallelism in that structure. Clearly, the ‘precedence relations’ of the real world — you must walk to the door before you go through it, for example — impose a high-level seriality on the flow of computation. However, within these high-level constraints, we shall see much room for parallel computation.

A few examples of how to use a symmetrical multi-micro-processor

Abstract: This paper presents an overview of an architecture of a multi-micro-processor architecture in which all processors are equivalent. The structure is characterized by a central memory and several caches, and is designed to avoid incoherent data. A fast mechanism of “subcontracting” between one processor and another is described.The execution of two simple programs under this architecture is studied. The parallel algorithms are described and compared with the original (sequential) algorithms; it is shown that the overhead remains small, few extra memories are necessary and synchronization do not slow down the execution unduly. Furthermore, the locality of the parallel algorithm is compared to that of the sequential algorithm and is found to be less good, but in a reasonable way. As well, an estimation of the cost of the coherence keeping mechanism is given using the difference between the miss ratio of the classical cache and the “coherence keeping cache”, respectively.

A modular memory scheme for array processing

Abstract: This paper presents a parallel memory scheme suited for pipelined processing units. The scheme is shown to be modular, relatively low cost and flexible. The scheme allows an arbitrary number of variables in the vector operations. It is shown that data alignment is handled by a simple interconnection scheme and that the interconnection scheme can be implemented in the memory modules. It is shown that the scheme facilitates efficient implementation of the Perfect Shuffle interconnection, hence the implementation of parallel algorithms using that interconnection scheme.

A Direct Approach to the Parallel Evaluation of Rational Expressions with a Small Number of Processors

Abstract: In this paper we construct algorithms and investigate the time required for the parallel evaluation of rational expressions using small numbers of processors. We define algorithms which compute a polynomial with n operations in 3n/(2p + 1) + Q(p2) time units with p processors and a general rational expression with n operations in 5n/(2p + 3) + 0(p2) time units. These algorithms are suitable for implementation on computers with restricted data access.

Microprocessor Based Parallel Computers and Their Application to the Solution of Control Algorithms.

Abstract: High-performance boats often require active stabilization using an embedded control system, but the marine environment is hard on electronics. Embedded computers must survive widely-ranging, noisy input power as well as high vibration, high-g shock, widely varying temperatures, and electromagnetic interference. Because typical commercial off-the-shelf (COTS) control technology is not designed for marine use, it is often unreliable and can even be dangerous on boats requiring stabilization. Therefore, to stabilize the 21.3 m technology demonstrator BLB-70 we used hydraulic actuation controlled, not by COTS technology, but instead by custom microcontroller-based hardware and software that we developed. Because microcontrollers are small, tough, and start up within milliseconds, they are often used in anti-lock braking and other demanding automotive applications. We overcame a traditional concern, their lack of floating-point throughput, by mounting five microcontrollers on a single board, all with distinct, specific tasks, in communication with each other using custom hardware and software. This paper explains the features and design principles of a marine-ready, multi-microcontroller ride control system and describes the successful use of such a system in stabilizing vessels such as BLB-70. Future development directions for this system are suggested.