Showing papers on "Parasitic element published in 1984"

Field-effect transistor

Abstract: PURPOSE: To reduce source parasitic resistance and increase breakdown strength between a gate and a drain by adopting a structure wherein carrier concentration is decreased only in a part of an active layer on the drain side. CONSTITUTION: The title transistor is constituted of a semiinsulative substrate 1, an active layer 2, electrodes of source, drain and gate 3-5, and a low concentration region 6. That is, the low concentration region 6 is arranged on the drain side. As to the low concentration region 6, the following are desirable for performance; the carrier concentration is lower than that of the active layer 2 or nondoped, and the thickness of the region is thinner than the depth tr of a recess. By this structure, source parasitic resistance can be sufficiently reduced, and charge quantity on the drain side decreases on account of existence of the low concentration region 6, so that breakdown strength between a gate and a drain can be increased. Thereby the reduction of source parasitic resistance and the increase of breakdown strength between a gate and a drain can be realized at the same time. COPYRIGHT: (C)1991,JPO&Japio

Circuit for detecting variation of resistance of a variable-resistance element

Abstract: A circuit for detecting the variation of resistance of a variable-resistance element comprises a pair of grounded-base transistors with their base electrodes provided with different base voltages and with their emitter electrodes connected to both terminals of the variable-resistance element so that the voltage between both terminals of the element is kept constant. The current density of the variable-resistance element does not vary when the resistance of the variable-resistance element varies, whereby the lifetime of the element can be prolonged.

Picosecond gain measurements in a GaAlAs diode laser.

Abstract: The amplification of injected optical pulses has been used to investigate the temporal response of the gain of a GaAlAs diode laser. Near-infrared dye-laser pulses of 4-psec duration were passed through the active region of the laser diode, which was driven by 80-psec current pulses. The measured gain-buildup time of 325 psec is likely determined by the electrical circuit parameters of the device, i.e., junction capacitance and resistance and parasitic inductance. The gain decayed with a time constant of 375 psec consistent with lateral carrier outdiffusion from the junction region.

Broad band microstrip antenna uses two-frequencies in common

Abstract: PURPOSE:To make the frequency band width broader, by arranging a sectorial parasitic element around an elliptic microstrip antenna. CONSTITUTION:An elliptic radiation conductor element 3 is provided on the upper side of a dielectric 2 and a ground conductor plate 1 is provided on the rear side. Further, two feeding points 7, 8 are provided on a major and a minor axis of the elliptic radiation conductor element 3. Plural sectorial parasitic elements 11, 11', 12, 12' are arranged around the conductor element 3 in a two-frequency common use type microstrip antenna constituted in this way. Thus, the frequency band width of coaxial feeding wires 9, 10 connected to the feeding points 7, 8 is increased as much as about >=3 times in comparison with the case not using the parasitic elements. Further, the coupling attenuation between the coaxial feeding wires is ensured for >=30dB.

Method of making junction field effect transistor

Abstract: A junction field effect transistor has a substrate forming a junction with a layer of semiconductor material which has a gate, a source and a drain therein. The thickness of the n-type layer underlying the source is substantially greater than that underlying the gate (for example the ratio of n-thickness below the gate to that below the source is 1 to 2.53) in order to reduce the parasitic resistance as compared to conventional JFETs.

A radiating device with a microstrip structure with a parasitic element

Abstract: A microstrip structure forming a resonator with losses is obtained on the basis of a dielectric plate (D), beneath which there is affixed an extensive metallisation forming the ground plane and on which there is affixed a metal slab (P10), with a rectangular configuration for instance. One edge of slab (P10) is provided with short circuit pins (CC) ending at the ground plane (PM). A perpendicular edge of slab (P10) is connected via a narrow metal channel (L11) to a further metal element (P11) which extends parallel to the edge concerned of the slab (P10) and over the same length as the latter. The supply is effected from below by means of a coaxial cable whose screening (CB) is connected to the ground plane, and core (CA) at a chosen point of slab (P10). This device is operating on two different frequencies on a narrow band for each one, with a particularly reduced size and an angular spread close to 180 DEG . Circular polarization is achieved by four units successively displaced by 90 DEG . An additional metal element (P12) may be provided at the end opposite to P11.

Semiconductor integrated circuit using vertical PNP transistors

Abstract: A semiconductor integrated circuit comprises a differential pair of transistors, a pair of constant current source transistors, an emitter resistor connected between the emitters of the differential transistors, and a load resistor coupled to the collector of one of the differential transistors. Each of the differential transistors and constant current source transistors is a vertical PNP transistor. In the semiconductor integrated circuit, therefore, each vertical PNP transistor has its collector coupled with a parasitic diode having a relatively large junction capacitance. The parasitic diodes are reversely biased when the circuit is operative. In order to prevent the frequency characteristic from being deteriorated due to the junction capacitance of the parasitic diodes, a resistor circuit, which forms a differentiating circuit together with the emitter resistor and the parasitic diodes, is connected between the cathodes of these diodes and a power source, whereby the differentiating time constant of this differentiating circuit is so adjusted as to become substantially equal to the integrating time constant of an integrating circuit including the load resistor and the parasitic diode.

Junction-type field effect transistor

Abstract: PURPOSE:To lower the parasitic resistance of a gate, and to increase a switching rate by forming a channel diffusion region of a shape that a low resistor is connected in parallel with a band-shaped gate diffusion region. CONSTITUTION:A pair of a band-shaped P type source diffusion region 15 and a band-shaped P type diffusion region arranged in parallel at a regular interval D1 are formed to the surface of an N type Si epitaxial layer 14. A plural row of P type channel diffusion regions 17 are formed to the surface of the layer 14 between these region 15 and region 16 so as to contain the region 15 and the region 16. A band-shaped gate diffusion region 18, which runs parallel with the region 15 and the region 16 and is shallower than the regions 17, is shaped at the position of equal distances from the region 15 and the region 16. According to such constitution, since a low resistor consisting of the layer 14 and an N type buried diffusion layer 12 in the lower section of the layer 14 is connected in parallel with the region 18, the parasitic resistance of a gate is reduced largely, and the switching rate of the titled junction type FET is increased.

Schottky-barrier-gate type field-effect transistor

Abstract: PURPOSE:To reduce parasitic resistance between a source and a drain by forming a gate electrode so that one part covers an inclined plane on the source side in a recessed section and separating the gate electrode from an inclined plane on the drain side CONSTITUTION:An N-GaAs layer 12 as an active layer is formed on a GaAs base body 11 A source electrode 13 and a drain electrode 14 are formed on the layer 12 in an ohmic manner A recessed section 15 forming recess structure is shaped by arrangement held by these electrodes 13 and 14 A gate electrode 16 for forming a Schottky-barrier is shaped in the recessed section 15 The electrode 16 is formed in arrangement in which at least one part covers an inclined plane 15b The electrode 16 is separated from an inclined plane 15c on the electrode 14 side According to such constitution, the value of parasitic resistance between a source and a gate can be inhibited to an extremely small value, and the characteristics of a proper FET can be obtained as the parasitic resistance is left as it is reduced