Showing papers on "Phase detector published in 1979"

Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery

Abstract: A significant problem in phase-locked loop (PLL) timing and carrier extraction is the initial acquisition. Very narrow loop bandwidths are generally required to control phase jitter, and acquisition may depend on an extremely accurate initial VCO frequency (VCXO) or sweeping. We describe two simply implemented frequency detectors which, when added to the traditional phase detector, can effect acquisition even with very small loop bandwidths and large initial frequency offsets. The first is the quadricorrelator, previously applied to timing recovery by Bellisio, while the second is new, and called a rotational frequency detector. The latter, while limited to lower frequencies and higher signal-to-noise ratios, is suitable for many applications and can be implemented with simpler circuitry.

Ultrasonic wave oscillator circuit with output meter

Abstract: An oscillation system, having a vibrator, a resonant bridge and a low resistance, oscillates at desirable frequencies by receiving an excitation signal amplified to a predetermined value by an amplifier. A detection feedback signal containing the resonant frequency of the vibrator is input to a phase shift circuit. The phase shift circuit adjusts the phase of the detection feedback signal and the excitation signal to satisfy the oscillation condition. The output signal from the phase shift circuit is input to a PLL comprised of a phase comparator, a low pass filter, an amplifier and a voltage controlled oscillator. The frequency of the output signal from the PLL follows the resonant frequency of the vibrator and is locked. Its output signal is applied to the amplifier which feeds the oscillation system. An analog multiplier circuit is fed with signals proportional to the current and voltage from the resonant bridge circuit, and outputs the product of these signals. The output of the multiplier circuit is rectified and applied to a DC meter for indicating power consumption of the vibrator.

Ultrasonic wave generating apparatus with voltage-controlled filter

Abstract: The present invention deals with an ultrasonic wave generating apparatus with voltage controlled filter, comprising a phase comparator which detects a shifted value from a predetermined phase difference between a driving voltage or a driving current of an ultrasonic transducer and a vibratory velocity signal, and a voltage-controlled band-pass filter which is controlled by the output of the phase comparator and which is provided in a feedback loop from the vibratory velocity signal to an input of a driving amplifier of the ultrasonic transducer, wherein the oscillating frequency is changed while following the resonant frequency of the ultrasonic transducer, so that stable operation is materialized without developing abnormal oscillation in subresonant frequencies and permitting very small following error.

Apparatus for deriving clock pulses from return-to-zero data pulses

Abstract: A phase-locked loop apparatus for deriving clock pulses from return-to-zero data pulses is disclosed. It includes a phase detector for computing the difference, in time, between that portion of a detected data pulse which occurs before a clock pulse edge and the portion after the clock pulse edge. The difference, once computed, is held for a long period thereafter and is used to drive a voltage controlled oscillator. The voltage controlled oscillator generates the clock pulses which are applied to the phase detector and which comprise the output of the apparatus.

Phase detector circuit using logic gates

Abstract: A phase detector circuit having four dominant type flip-flop circuits and at least one logic gate. The phase detector circuit is responsive to changes of two input signals, and produces output signals related to the relative phase of the input signals having duty cycle. The output signals have a predetermined level only for the period the phases of the input signals differ. When the phases of the input signals are the same, the output signals of the phase detector circuit will be at another level.

Closed loop stepper motor circuitry without encoder

Abstract: Stepper motor control circuitry including a phase locked loop circuit formed by a phase detector outputted to a filter and a voltage controlled triangular and square wave generator which has a frequency control input terminal connected to the output of the filter and which provides a square wave on an output thereof connected as an input to the phase detector. An oscillator drives the phase detector, and the outputs of the generator are connected as inputs to a pulse width modulated driver which has its outputs connected to the coils of the stepper motor. A differential amplifier is connected across one of the coils of the motor, and a balanced modulator synchronous detector or multiplier has two inputs one of which constitutes an output of the differential amplifier and the other of which is a connection to the square wave output of the generator. The output of the multiplier constitutes an error signal which is supplied to a summing junction between the filter and generator so that, upon the application of an instantaneous load to the stepper motor, the error signal causes a very quick return to normal speed of the motor.

Phase locked loop system with improved acquisition

Abstract: A phase locked loop system having improved acquisition time is particularly suitable for use in a television receiver with frequency synthesizer tuning. A conventional phase locked loop is modified by the addition of a pair of transmission gates and a frequency discriminator/detector. The transmission gates are normally open, and the phase locked loop system operates in a conventional manner. When a programmable frequency divider connected between the output of the voltage controlled oscillator and the input to the phase locked loop phase comparator has its division ratio changed to select a new channel, the frequency discriminator, which also is connected to the output of the programmable frequency divider, applies an appropriate gating signal to one or the other of the transmission gates to close that gate. The two gates are connected respectively to sources of direct current potential which operate rapidly to force the maximum control signal on the voltage controlled oscillator in the desired direction to produce acquisition until the phase locked loop is nearly locked. When the frequency at the output of the programmable frequency divider comes within a range which is a predetermined amount above or below the desired center frequency of the frequency discriminator, the output of the frequency discriminator terminates, opening the one of the transmission gates which previously was closed to return the system back to operation as a conventional phase locked loop system.

Method and apparatus for modulating a phase locked loop

Abstract: A phase locked loop provides frequency modulation over an extended frequency range by summing a modulation signal with the loop signal at two separate points within the loop. The modulation signal is directly applied to the control input terminal of the voltage controlled oscillator. In addition, the modulation signal is processed to compensate for the transfer functions of loop components, and the processed signal is summed with the loop signal at an additional point between the output terminals of the phase detector and the lowpass filter of the loop. The processing of the modulation signal consists of preshaping of the signal to compensate for the transfer functions of loop circuitry located between the voltage controlled oscillator and the summing junction.

Video signal time base error correction circuit

Abstract: A system for compensating and correcting errors in the time base of video signals read from a video disc in which the errors are corrected first coarsely in response to phase differences between horizontal sync signals of the video signals following which a fine correction is made in response to measured phase differences of burst signals of the video signal. A first phase detector produces an output signal in response to phase differences between the burst signals and an output of a reference frequency generator operating at the burst frequency. A second phase detector produces an output signal in response to phase differences between the horizontal signals and the reference signal divided down by a predetermined factor. The output signals of the two phase detectors are summed and then applied to the control input of a variable delay line which adjusts the delay time and hence phase errors in the video signal accordingly.

Laser beam recording system

Abstract: In a laser beam recording system employing a rotating polygonal mirror for deflecting a recording light beam and a read-out light beam for synchronization, a linear encoder is used to generate a video clock signal in synchronization with the photoelectric pulse signal obtained through the linear encoder. In the video clock signal generator, a clock signal is divided into 1/n where n is an integral number to provide a reference pulse signal to be compared with the photoelectric pulse signal. The displacement of the phase of the photoelectric pulse signal from the reference pulse signal is detected and is corrected by a phase comparator. Thus, a video clock signal having a frequency of n-times as large as that of the photoelectric pulse signal is generated.

Induction balance metal detector with ferrous and non-ferrous metal identification

Abstract: An induction balance metal detector circuit includes a receiver coil output which is connected to one input of a unique phase detector circuit. The reference transmitter coil signal is connected to a second input of the phase detector. The phase detector comprises circuitry which provides an output equal to the smaller of the two input signals. The output is doubled and integrated, then compared to a current indicative of the integrated reference signal in a differential amplifier. The output of the differential amplifier is passed through a dead band and used to excite a first indicator in response to phase difference between the inputs to the phase detector indicative of the location of ferrous metals. A second indicator is excited in the event the phase difference indicates the presence of non-ferrous metals. A balance and threshold control is established between the transmitter and the receiver coils in order to adjust the phase and amplitude of the received signal. A feedback loop is established between the ferrous metal output and the threshold and the balance control. The ferrous metal output is integrated to provide an indication of mineralized soil in the environment. This integrated output is utilized to change the impedance at the receiver coil in order to null out the effects of the mineralized soil. The circuitry is adapted for use in integrated circuit form.

Apparatus and method for achieving acquisition and maintaining lock in a phase locked loop

Abstract: A voltage controlled oscillator (VCO) and reference oscillator are connected in a phase locked loop with a first phase detector, loop switch, and acquisition sawtooth sweep circuit. A second phase detector and fast integrator circuit are connected to the VCO and reference oscillator in quadrature relation with respect to the first phase detector. As the acquisition sweep circuit sweeps the VCO, the fast integrator produces a signal whose magnitude increases as the swept VCO frequency approaches the frequency needed for the phase locked loop to achieve phase lock. When this signal magnitude exceeds a predetermined threshold, an output control signal is produced. This output control signal causes the loop switch to close and make the phase locked loop operational. A delay circuit is connected to the second phase detector and fast integrator. The delay circuit produces a delayed output at a predetermined time after the control signal is produced. The delayed output prevents the acquisition sweep circuit from further sweeping after the phase locked loop is operational. The delayed output can also be used to energize other apparatus, such as a radio transmitter. If the phase locked loop includes a mixer or divider which may produce an image or harmonic frequency that could cause erroneous phase lock, a complementary or inverted output can be derived from the second phase detector, and applied to a slow integrator. If the slow integrator output exceeds a predetermined threshold, it opens the loop switch and disables the phase locked loop. This permits the acquisition sweep circuit to operate until the proper frequency is acquired for proper operation by the phase locked loop.

Frequency synthesizer tuning system for television receivers

Abstract: A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A programmable frequency divider counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator in the tuner also is applied. The phase comparator output provides a tuning voltage for controlling the tuning of the local oscillator. A microprocessor is used to control the count of the programmable frequency divider and initially to set a count corresponding to the selected channel in a counter connected between the output of the local oscillator and the phase comparator. The AFT discriminator signal is used to sense the presence or absence of a properly tuned condition and to control the operation of the microprocessor for establishing the count in the programmable frequency divider counter. For a localized search, the microprocessor may drive the programmable frequency divider counter to a predetermined maximum count and then step back a fixed number of counts to a lower count and resume counting in the original direction; so that even if the AFT discriminator output is in an ambiguous condition, proper tuning can be achieved. However, if the AFT discriminator output produces the correct tuning direction information initially, the programmable frequency divider is adjusted step by step to the appropriate larger or smaller count that corresponds to correct tuning.

Digital frequency-phase comparator

Abstract: A digital frequency-phase comparator includes a bistable element responsive to first and second frequency input pulse signals for generating a phase error signal, a circuit which includes second and third bistable elements responsive only to the leading edge transition of the input pulse signals in the presence of the outputs from the first bistable element to generate frequency error signals, and a circuit which combines the phase and frequency error signals to provide a triple state output.

Variable speed motor system

Abstract: An electronic system for controlling the speed of a shaded-pole single-phase induction motor provides increased power during speed increase and automatic braking during slowdown by regulation of half-wave D.C. braking current applied to the motor. Speed control during normal operation, and braking control during slowdown and stopping, are implemented by means of dual feedback loops interactively connected to the gate electrode of a triac in the A.C. current line of the motor. The speed control loop utilizes a frequency/phase detector to adjust the time delay of triac gating relative to the zero crossing points of each half-cycle of A.C. voltage until the tachometer-sensed speed of the motor corresponds to a desired speed set by a voltage controlled oscillator. The braking control loop adjusts the time delay of the triac gating relative to the zero crossing points of every alternate half-cycle of A.C. power thus decelerating the motor by an impressed half-wave pulsed D.C. current.

Phase-locked loop speed control system using programmable counter for frequency pulling

Abstract: A phase-locked loop system for controlling the speed of a motor or the like comprises an oscillator generating clock pulses or the like comprises a programmable frequency divider receptive of clock pulses for delivery of output pulses at a frequency which is an integral submultiple of the clock frequency, the integral submultiple being variable as a function of external supplied digital signals. A phase comparator compares speed related pulses. A transducer generates pulses at a repetition frequency related to the speed of the motor which is compared in the phase comparator with the output pulse from the frequency divider for driving the motor. A programmable binary counter is provided which is reset in response to the beginning of each period of the speed related pulses for counting the clock pulse. A logic gate circuit is connected to the counter stages of the programmable counter to define a range of pulse counts to generate motor control voltage signals when the count falls outside of the defined range.

Phase detector for phase locked loops

Abstract: A phase locked loop circuit employing a first edge detector consisting of an exclusive OR gate and flip flop circuit feeding by way of a NAND gate, an up counter and a second edge detector of like kind feeding also by way of a NAND gate into a down counter. Both counters feed into an added which provides a signal to a decoder representing the phase difference between the input phase and the output phase signal. The phase processing system provides positive rapid pull-in over the entire frequency range capability of the VCO, which allows narrow bandwidth loops to track rapid rates of frequency change without loss of lock and with great accuracy.

Ghost cancellation circuit system

Abstract: A ghost cancellation circuit system comprises an amplifier for forming an output signal of a composite wave of a direct wave and a ghost wave; a carrier wave extracting circuit for extracting the carrier wave having the reference phase from the output signals of the amplifier; phase shifting means for generating a detection axis signal having the specific phase of the output of the carrier wave extracting circuit; a pair of phase detection circuits for a phase detection of the output of the amplifier by the detection axis signal of the phase shifting means or the carrier wave extracting circuit, and a delay circuit for forming the output in delay for a time substantially equal to the delay time of the ghost wave by receiving the output of the pair of phase detection circuits through a pair of coefficient circuits, whereby at least a specific component of the ghost wave is cancelled by summing the output of the delay circuit to the output of the phase detection circuit.

Detection Performance of Hard-Limited Phase-Coded Signals

Abstract: The performance of a complex phase-coded waveform digital processor with hard-limiting constant false-alarm rate (CFAR) is presented. Processing losses relative to ideal matched-filter performance are computed and verified by hardware measurement. The losses considered include the consequences of hard limiting, envelope algorithm implementation, range cusping, and the associated effects of code length, IF filter bandwidth, and in-phase and quadrature channel phase offset. The range resolution properties of two closely spaced targets are also considered.

Digital phase comparing apparatus

Abstract: A digital phase comparator, to be used in a phase locked loop, for example, comprises a first and second input signal terminals receiving a first and second input signals, respectively, the phases of which are to be compared, and a pair of first (710) and second (720) delay flip-flops. The first input signal terminal is connected to a clock terminal (CL1) of the first delay flip-flop and a reset or set terminal (R2) of the second delay flip-flop. The second inputterminal is connected to a set or reset terminal (R1) of the first delay flip-flop and a clock terminal (CL2) of the second delay flip-flop. An inverted or non-inverted output terminal of the first delay flip-flop is connected to a data terminal (D2) ofthe second delayflip-flop. An inverted or non-inverted output terminal of the second delay flip-flop is connected to a data terminal (D1) of the first delay flip-flop. An output signal associated with the phase difference between the first and second input signals is obtained from the output terminals of the first and second delay flip-flops.

Insertion loss and phase shift measurement system and method

Abstract: Insertion loss measurement at microwave frequencies is achieved using an improved IF substitution technique wherein the IF test signal is applied to a feedback loop which generates a feedback signal to null out the test signal. A precision calibrated attenuator in the path of the feedback signal is adjusted to achieve the null, and the difference between attenuator settings with the device under test in and out of the microwave test signal path is a measure of the insertion loss of the device under test. In one embodiment the difference signal between the IF test signal and the fed back null signal is divided into amplitude and phase components which are integrated and used to control the attenuation and phase shift, respectively, of a reference signal at the IF test signal frequency, the controlled reference signal comprising the fed back null signal. In another embodiment the amplitude and phase components are filtered at d.c., restored to IF, and recombined before being fed back as the null signal. Still another embodiment steps the difference signal is stepped down to the audio frequency range in successive steps and is filtered at the audio level before being stepped back up to IF and fed back. Any of these embodiments can be employed in a dual channel system, one of which contains the device under test, wherein the fed back null signals are compared in phase to determine the phase shift introduced by the device under test. A novel phase shifter is disclosed wherein the 360° limitation of unambiguous phase detection is overcome.

Phase synchronous oscillator

Abstract: PURPOSE:To prolong the free-running holding time without varying an output frequency even if an input signal is cut off, by providing a counter, D/A converter, adder, etc. CONSTITUTION:Phase difference detecting counter CNT6, D/A converter 7, adder 9, etc., are provided. Once input signal (a) is cut off, phase comparator 1 outputs a rectangular wave signal with a period twice that of output signal (b). On the other hand, a digital value stored in counter 6 is converted 7 into an analog value, which is applied via AND gate 8 to circuit, where it is added to the output of LPF2. Thus, circuit 9 outputs a voltage obtained by adding a control signal corresponding to a center frequency before voltage control osicllator VCX03 varies in characteristics to a signal corresponding to a stationary phase error after the characteristic change and before a self-scan, and the voltage is applied to oscillator 3 to control its oscillation frequency. Therefore, oscillator 3 is applied with the same voltage as before the free-running start and the oscillation frequency never changes, prolonging greatly the free-running holding time.

Phase locked loop carrier recovery circuit with false lock prevention

Abstract: A carrier recovery apparatus for phase modulated waves including phase-locked loops is operable to prevent false locks. The apparatus includes a clock recovery circuit which generates a signal in response to a modulated carrier, a first phase comparator responsive to the modulated carrier and the output of a VCO, a second phase comparator responsive to the first phase comparator and the clock signal, and a control device for superimposing the low frequency component of the output of the second phase comparator on the output of the first phase comparator or a loop filter which controls the VCO.

Charged coupled device time base corrector system

Abstract: An improved charged coupled device time base corrector system to compensate for a change in the phase or frequency of input video signals, as occurs in the playback of a video tape recorder, by changing the nominal delay through the corrector, comprising, in combination, an input feedback circuit and an output feedback circuit. The input feedback circuit includes two cascaded infinite gain circuits, an infinite gain phase detector followed by an infinite gain voltage amplifier which gives an error voltage that controls the frequency of the voltage controlled oscillator (VCO) utilized to control the system delay. The output servo loop always adapts itself to the input error voltage. The VCO is thereby driven at a rate of change of its frequency proportional to the incoming error signal. .

Afpc phase detector with no output from alternate sync pulses

Abstract: A gating circuit coupled to the phase detector of an AFPC loop prevents response of the phase detector to alternate sync pulses during the equalizing and vertical sync pulse interval.

Digital phase-locked loop

Abstract: In a digital phase-locked loop, preferably for bit rate regeneration in synchronous data transmission systems, transmitting from a sender to a receiver redundantly coded information possibly modulated in a suitable mode there is an addition circuit connected to one control input of a digital controlled oscillator incorporated in the loop. The addition circuit adds control signal contributions from a phase comparator circuit of the loop and an error detector. This error detector is connected to an output of the receiver data detector, and examines whether the input signal in the circuit has the inherent redundant properties expected taking into account the signal coding. When this is not the case, a pulse-shaped control signal is fed to the addition circuit.

Television horizontal afpc with phase detector driven at twice the horizontal frequency

Abstract: A television phase-lock (AFPC) loop is used to maintain a horizontal oscillator in synchronism with horizontal synchronizing signals in the presence of noise. The AFPC loop includes a phase detector and a controlled oscillator. The synchronizing signals are applied to one input of the phase detector and the oscillator output is applied to the other phase-detector input. The phase-detector output is coupled back to the oscillator control input to maintain the oscillator output in frequency synchronism. During the vertical synchronizing and equalizing pulse intervals, the synchronizing signals applied to the AFPC phase detector increase in frequency. The increase in frequency may decrease the AFPC loop gain or unsynchronize the loop. This effect is overcome by providing a second output from the horizontal oscillator at a frequency higher than, but related to the frequency of the desired output, and using the higher frequency to drive the phase detector. A phase ambiguity results from the higher-frequency control. The phase ambiguity is resolved by a controlled switch which couples the high-frequency oscillator output to the phase detector during the vertical synchronizing and equalizing pulse intervals and couples the desired oscillator output signal to the phase detector input at other times.

Digital signal recorder

Abstract: PURPOSE: To make it possible to record digital signals differing in sampling frequency by making recording density constant by adjusting the drive speed of a recording medium when the sampling frequency varies. CONSTITUTION: In recording, the comparison output of phase comparator 26 is applied as a driving voltage to capstan motor 28 via driving amplifier 29. The detection output of a rotary phase detector turning together with motor 28 in a body is supplied to circuit 26 by way of amplifier 31 and recording-side terminal 25r of recording/reproduction change-over switch 25. As a result, the rotary phase of motor 28 is locked on the basis of the leading edge of divider 18. Therefore, a fundamental clock frquency from clock generating circuit 16 varies and when the frequency of the output pulse of divider 18 varies, the rotational frequency of motor 28 also varies correspondingly, so that the shortest wavelength of a magnetic tape in recording will be constant without reference to the value of the sampling frequency. COPYRIGHT: (C)1980,JPO&Japio

Fault locating arrangement for a two-way repeatered transmission link

Abstract: A fault locating arrangement for a two-way repeatered transmission link comprising a source in one of the terminals to transmit a unique signal in a first transmission direction from the one of the terminals to the other of the terminals through the repeaters, and a first unique signal detector, a second unique signal detector and logic circuitry disposed in at least the other of the terminals and each of the repeaters. The first unique signal detector is coupled to the first transmission direction, the second unique signal detector is coupled to the opposite transmission direction and the logic circuitry is coupled to the first and second unique signal detectors such that, when the unique signal traveling in the first transmission direction is detected, a loop connection is established for the unique signal from the first transmission direction to the opposite transmission direction and the unique signal is transmitted in the first transmission direction beyond an associated one of the repeaters. The logic circuitry breaks the loop connection when the unique signal is detected traveling in the opposite transmission direction and maintains the loop connection when the unique signal is not traveling in the opposite transmission direction. A phase comparator disposed in the one of the terminals responds to the unique signal transmitted in the first transmission direction and received from the opposite transmission direction to provide an indication of the location of a fault in the transmission link.

Vertical synchronization circuit for a cathode-ray tube

Abstract: A vertical synchronization circuit for a cathode-ray tube comprises an oscillator for generating, in response to the horizontal synchronizing signal of an input video signal, clock pulses at twice the horizontal scanning frequency; a counter for counting the clock pulses and producing a first pulse when the pulse count reaches 525; a waveform shaping circuit receiving the vertical synchronizing signal of the input video signal and the clock pulses for producing a second pulse; a circuit for shaping the first pulse to produce a phase-comparing pulse; a phase comparator for comparing the phases of the phase-comparing pulse and the second pulse; a switching circuit controlled by the phase comparator for supplying the second pulse to the counter as a reset pulse when the phase comparator does not detect continuous coincidence during a specific vertical scanning period and for supplying the first pulse to the counter as a reset pulse when the phase detector detects continuous coincidence during the vertical scanning periods; and a circuit for shaping pulses produced by the counter in synchronism with the received vertical synchronizing signal.