Showing papers on "Pipeline (computing) published in 1978"

Concurrent task and instruction processor and method

Abstract: A processor and method for concurrent processing of tasks and instructions are disclosed. The processor is basically a multiple instruction, multiple data stream (MIMD) digital computer that utilizes pipelining for control and function units, but avoids precedence constraint penalties. Task and instruction processing is carried on concurrently through the use of a snapshot taken of the next process status words (PSWs) to be serviced for each active task, the pointers for which are stored in task first in-first out buffers (task FIFOs). The PSWs, along with their parent task status words (TSWs), are placed into the control pipeline one at a time and serviced, after which each PSW pointer is placed back in the task FIFO from where it was taken. After all process status words of the snapshot have been entered into the control pipeline, a new snapshot is taken and the PSWs processed in the same manner. Instruction execution is carried out as the TSW/PSW pair proceeds through the control pipeline, during which time the required data operations are carried out by pulling operands from a memory unit, as required for execution of that particular instruction, and causing the same to be sent to the function units after which the results are placed in the memory unit. For interprocess data transfers, synchronization is accomplished through use of hardware implemented semaphores called a scoreboard. In addition, passage of data between processors and memories other than those associated, or local, memories, is through a memory switch.

Data processing system with an enhanced pipeline control

Abstract: A data processing system, for executing each instruction, by carrying out a plurality of successive partial processing operations, begins to process the first partial processing operation of an instruction succeeding a defeat overlap instruction before execution of the defeat overlap instruction is finished in response to the detection that a predetermined number of machine cycles is further required for the complete execution of the defeat overlap instruction.

Pipeline bending method

Abstract: A method for the controlled bending of a submerged pipeline is disclosed. The section of the pipeline which is to be bent is slightly elevated off the sea floor, preferably by buoys attached to the pipeline along its length. The end of the elevated section of pipeline is pulled in to the desired point of termination while a drag force is simultaneously applied to the elevated portion of the pipeline. The applied drag force should be sufficient to create a bending moment which causes the pipeline to bend along a well defined arc. Preferably, dragging means such as chains, cables, or clump weights extending from the pipeline to the sea floor are used to impose the necessary drag force on the pipeline and to control elevation of the pipeline above the sea floor.

Offshore pipeline electrical survey method and apparatus

Abstract: A method and apparatus for conducting offshore pipeline electrical surveys is characterized by initially locating and marking the pipeline, traversing the length of the pipeline towing a reference electrode in close proximity to the structure, providing a supply of wire having one end electrically and mechanically connected to the pipeline at a reference location, playing out the wire along the length of the pipeline through a distance measuring device while transporting the supply of wire and towing the reference electrode, and measuring and recording the potential difference between the reference electrode and pipe either continuously or at spaced test locations along the length of the structure. The method and apparatus are further characterized by alternately connecting and disconnecting an electrical power source to the pipeline at the reference location, measuring and recording the potential difference in both connected and disconnected modes at the test locations, and measuring and recording the depolarization and/or polarization times when the power source is disconnected and/or connected, respectively, to the pipeline.

Two-Dimensional Microprocessor Pipelines for Image Processing

Abstract: Two-dimensional arrays of microprocessors are considered for the implementation of image processors that are formulated according to a certain state-space model. The microprocessors are totally synchronized—operating with the same clock and executing the same instructions, communicating with each other through local memory units. This allows the use of such an array as a pipeline for the processing of successive images or sections of one image, to achieve a relatively fast effective speed.

Design of arithmetic elements for Burroughs Scientific Processor

Abstract: The design criteria and implementation of the Arithmetic Element (AE) of the Burroughs Scientific Processor, a vector machine intended for scientific computation requiring speed of up to 50 million floating-point operations per second, is discussed. An array of 16 AEs operate in lockstep mode, executing the same instruction on 16 sets of data. The 16 AEs are one stage in a pipeline which consists of 17 memory modules, an input alignment network, and an output alignment network. The AE itself is not pipelined. It can perform over one hundred different operations including a floating-point addition, subtraction and multiplication, division, square root, among the others. Eight registers are provided for the storage of intermediate values and results. Modulo 3 residue arithmetic is used for checking hardware failures.

Apparatus for inspecting a pipeline for leaks

Abstract: A method and apparatus for automatically adjusting the gain of an ultrasonic device for inspecting a pipeline for leaks. The ultrasonic device is designed to pass through the interior of a pipeline and record noise produced by fluids leaking from the pipeline. The response of the device is adjusted automatically by controlling the gain of the amplification in response to the strength of a signal received from an ultrasonic generator positioned outside the pipeline.

Line break detector

Abstract: A break detector by which an internal pressure of a pipeline is detected and a changing rate thereof is detected and compared with a desired value and further, when the desired value is greater than the changing rate, a ramp output generates and is compared with the desired value and when the value becomes equal to same, a break signal is generated to cause fluid flow in the pipeline to stop, thereby serious pollution problems due to the occurrence of pipeline burst are prevented. The break detector according to the present invention can be used in poor environmental conditions and has high accuracy in operation thereof as well as simplicity and ease in adjustment, installation and maintanance regardless of the type of fluid flowing through the pipeline.

A methodology for programming a pipeline array processor

Abstract: In this note a recursive filter implementation is discussed, analyzed and programmed in the most efficient way for the FPS-AP120B array processor.The purpose of this note is not only to demonstrate a good technique for programming this filter (even though it is a noble goal by itself), but to demonstrate the methodology involved.The FPS-AP120B array processor was chosen because it has microprogrammed control parallel pipeline architecture, which is typical for a wide class of high performance array processors.

Design of a pipeline route

Abstract: This paper presents a mathematical model for the problem of designing an optimal pipeline route. Two approaches are suggested. First, a heuristic method that decomposes the problem in a serie of one-variable optimization problems, a classical shortest route problem and finally a problem of designing optimally a pump-pipe system in serie, is outlined. Second, an algorithm to obtain the optimal solution based in the idea of embedding a dynamic programming algorithm in a shortest route algorithm is suggested.

Reconfigurable Pipeline Systems

Abstract: Systems with pipeline processing capabilities, processors whose computational subsystems are divided into several distinct stages, each of which may be working with an independent set of data at the same instant of time, are one attractive solution to the demand for faster and more cost effective computers. In addition, several of the existing pipelined machines have facilities for a limited amount of restructuring of available resources to provide a system which is more suitable for the efficient execution of a particular problem. The amount of restructuring, or reconfiguration, varies from system to system. The type of reconfiguration, either a reconfiguration of an actual functional unit or a reconfiguration of the information flow between several functional units, varies as well. The reconfigurable aspects of the architecture of several pipelined machines are presented. Performance gains when restructuring is allowed are also examined. Finally, there is a discussion of some possible future reconfigurable pipeline systems.

Pipeline control system

Abstract: PURPOSE:To improve the execution processing capability of instructions, by performing the pipeline processing for preparation of respective operands of instuctions besides the pipeline processing between instructions. CONSTITUTION:Instructions I1-I3 have two operands respectively. In the first cycle t1, instruction words of the instruction I are read IF . In the next cycle t2, the OP code part and an addressing designation part of the first operand are decoded. In the next cycle t3, the effective address of the first operand is calculated in accordance with the decode result, and an addressing designation part of the second operand is decoded. In the next cycle t4, the first operand is ferched, and the effective address of the second operand is calculated. Thus, the pipeline processing for preparation of respective operands of instructions is performed to improve the execution processing capability of instructions.

Pipeline internal coating machine

Abstract: Pipeline internal coating machine is wheeled carriage with spray tube at front supported inside by three equispaced wheels

Availability ratio for performance of pipeline components in two-phase flow

Abstract: A new method is presented which uses the steady flow availability function to analyze the efficiency with which energy can be transmitted in a pipeline. It is suggested that the availability approach can be used to compare the performance of all types of pipeline components such as bends, diffusers, etc., and their effect on the power available at the power turbine.

High-Performance Parallel Processors

Abstract: This paper is a survey and tutorial of high-performance parallel processors. It covers the subjects of multiprocessors, pipeline processors, array/associative processors and scientific processors. Architecture summaries are provided.

Real-Time Synthetic Aperture Radar Data Processing For Space Applications

Abstract: Range and azimuth correlation in the time domain using current state-of-the-art CCD LSI technology provides a potentially practical means of achieving real-time pipeline processing of SAR images for future space missions. The proposed range correlator approach, using already demonstrated CCD transversal filtering techniques, will require very little power: less than 10 watts per Seasat-type 20-km processing module. The azimuth correlator architecture is considerably more demanding since it requires a large number of parallel chips (1020 for a Seasat-type 20-km module) to achieve a real-time processing capability.