Showing papers on "PowerPC published in 1993"

The Power PC 601 microprocessor

Abstract: The PowerPC 601 microprocessor, the first of a family of processors based on the PowerPC architecture, is described. The general-purpose processor contains a 32-Kb cache and a superscalar machine organization that allows dispatch and execution of up to three instructions each clock cycle. The bus interface and storage control mechanisms can be configured for a wide range of system designs, from low-cost desktop personal computers to high-performance multi-processor systems. The PowerPC architecture, machine organization, chip packaging technology, and performance are discussed. >

The PowerPC 601 microprocessor

Abstract: A highly integrated, single-chip microprocessor is described that combines a powerful reduced instruction set computer (RISC) architecture with a superscalar machine organization and a versatile, high-performance bus interface. The PowerPC 601 microprocessor contains a 32-kbyte cache and is capable of dispatching, executing, and completing up to three instructions per cycle. The bus interface can be configured for a wide range of system bus interfaces, including pipelined, nonpipelined, and split transactions. In addition, the processor is equipped with features suitable for symmetric multiprocessing applications. The result is a cost-effective, general-purpose microprocessor solution that offers very competitive performance. >

PowerPC: a performance architecture

Abstract: The authors provide an overview of the PowerPC architecture Some of the issues and decisions that helped shape this architecture are discussed This architecture has incorporated the needs and ideas of leading software, system, and microprocessor design engineers With input from this broad spectrum, the designers of PowerPC emerged with an architecture built for high-performance first-generation implementations, while maintaining room for maximum expandability In addition, the PowerPC architecture was specifically designed to make it possible to implement high-performance single-chip processors This allows for a balance between maximum performance, ease of manufacturability, and low price >

The PowerPC 601 design methodology

Abstract: To produce a marketable PowerPC microprocessor on a short development schedule, an appropriate balance was needed between a fully customized methodology and a standard cell approach. We compiled a single model of each logic partition separately for logic synthesis and for simulation. Synthesis transferred the model to a gate-level implementation and applied timing correction transforms to reach the users' timing assertions. Floor-planning and wiring was assisted by an automated tool. Billions of cycles were run in testing the implementation against the PowerPC architecture specification. Behaviorals were written and built into the model to test the chip as it might appear in a system configuration. Careful adherence to this methodology led to a successful first pass of silicon, leaving the second iteration for additional customer requests. >

Multiprocessing aspects of the PowerPC 601

Abstract: The authors describe the multiprocessing capabilities of the PowerPC architecture and the first implementation of that architecture, the 601 microprocessor. The architected multiprocessing (MP) facilities of PowerPC are presented, and the 601 microarchitecture and system interface are discussed in the context of multiprocessing support. It is pointed out that the PowerPC architecture and the 601 seek to advance the state of the art for multiprocessing by providing a building block that addresses full MP functionality and MP performance in a way that has little risk for the system designer and with performance features heretofore unavailable in the microprocessor marketplace. >