Showing papers on "Program counter published in 1978"

Instruction set modifier register

Abstract: An instruction set modifier register, comprising one or more bistable latches which are loadable under program control, is provided for use in a processor in conjunction with an instruction register. An instruction decoding circuit and an instruction execution control logic circuit, responsive to both the instruction register and the instruction set modifier register, generate a first set of control signal combinations corresponding to a first instruction set when the instruction set modifier register is in a first state and generate a second set of control signal combinations corresponding to a second instruction set when the instruction set modifier register is in a second state. The processor is thus able to execute more than one set of instructions, utilizing the same instruction decoding circuitry and instruction execution control logic circuitry.

Multi-processor for simultaneously executing a plurality of programs in a time-interlaced manner

Abstract: A computer processor is described capable of simultaneously executing a plurality of programs. It accomplishes this by utilizing the next instruction select elements of a processor to select the next instruction for one program, while the data processing elements of the processor are executing an instruction of another program. The processor includes in addition to the next instruction select and data processing elements normally found in a microprocessor, additional program dependent elements for each of the plurality of programs to be processed. That is, it includes for each of the programs to be processed, a program memory allocation, a program address register, and the non-shared data storage registers, such as accumulators.

Address generating system

Abstract: A data processor includes a base register for a base address modification and a program counter for a relative address modification. An instruction executed in the data processor includes an operation code, a first operand, an address modification judgement bit, an index address modification field, a base address modification field and a displacement. When the instruction is fetched, it is arranged in an address modification and a base modification according to the address modification judgement bit. In the case of the relative address modification, the contents of the program counter is added to the contents of the displacement. In the case of the base address modification, the contents of the base register specified by the base address modification field is added to the contents of the displacement. In the relative address modification and the base address modification, the contents of the general register specified by the index address modification is added to the results of the addition, thereby to form an effective address.

Microprocessor having instruction fetch and execution overlap

Abstract: A microprocessor having separate bidirectional instruction and data busses is disclosed which allows the fetching of instructions from a program memory to be overlapped with the execution of instructions previously fetched. Program instructions are stored in an internal read-only-memory and/or in an external read-only-memory. Variable data is stored in an internal register array. During a given machine cycle, a data word in the register array can be transferred to an arithmetic-logic unit by a bidirectional data bus. The result of the operation performed by the arithmetic-logic unit can be transferred by the data bus back to the register array and stored in the selected location during the same machine cycle. Simultaneously, the contents of a program counter are transferred by a bidirectional instruction memory bus to the program memory to access the instruction to be executed on the following machine cycle. The addressed instruction is transferred from the program memory by the bidirectional instruction memory bus to the microprocessor and is stored to be decoded and executed on the following machine cycle.

Microinstruction storage units employing partial address generators

Abstract: A microcontroller having a novel addressing arrangement for addressing a storage means containing microinstructions is disclosed. The microcontroller has a fixed machine cycle time for executing each instruction and is arranged to fetch the next instruction during the execution of the current instruction. Branch, conditional branch and non-branch type of instructions are executed. The means for executing instructions is characterized by a plurality of instruction addressable data sources which are selectively connected to the input of the ALU register during the input phase of the machine cycle and a plurality of instruction addressable data destinations which are selectively connected to the output of the ALU register during the output phase of the machine cycle. The means for fetching the next instruction is characterized by a plurality of partial address generators, one of which is the ALU register employed to transfer data from a source to a destination. Control means responsive to the contents of an instruction register decoder supplies appropriate control signals at predetermined times to cause the transfer of address signals from the partial address generators to the address register to initiate readout of the next instruction from the instruction storage means during the execution of the current instruction.

Microprocessor having plural internal data buses

Abstract: A microprocessor comprises an internal address bus having a first portion (2,4) having a plurality of conductors carrying the low order address byte and a second portion (10) having a plurality of conductors for carrying the high order address byte. The microprocessor further comprises a plurality of registers, including an incrementor (12,13), a program counter (14,15), a temporary register (16,17), a stack pointer (18,19), an index register (20,21), and an accumulator (22,24), each comprising a pair of 8-bit registers for temporarily storing information. An arithmetic logic unit (28) performs computational operations on digital information within the microprocessor. The microprocessor includes a pair of internal data buses (6,8) each having a plurality of conductors for conducting digital information within the microprocessor. Means are provided for coupling selected ones of the registers, or the high or low order portions thereof, to the first and second data buses. The provision plural internal data buses permits a greater number of transfers of digital information to occur within the microprocessor during each machine cycle. The result is more efficient microprocessor operation and higher throughput.

Address conversion unit for data processing system

Abstract: An address conversion method and unit for a data processing system is disclosed which converts logical addresses into physical addresses representative of plural addressable storage locations. Each instruction includes a portion indicative of a first or second kind of instruction. In the case where an instruction is of the first kind, the content of a register in a first base register arrangement specified by the instruction is added with an address part of the instruction to produce a logical address. In the case where an instruction is of the second kind, on the other hand, the content of a register in a second base register arrangement specified by the instruction different from the first base register arrangement is juxtaposed with an address part of the instruction to produce a logical address.

Computer for directly executing a program including a plurality of structured blocks

Abstract: A computer which executes a program made up of a plurality of blocks comprises a program counter which designates an address of an instruction to be executed, first and second registers that stores entry addresses of first and second blocks respectively of the program, and a push down stack that stores an entry address of a third block of the program. The instruction designated by the program counter causes the reading out of data from a main memory device so as to read out the contents of one of the first, second or third blocks of the program from the main memory device for execution. The designated instruction causes the reading of one of the entry addresses stored in the first and second registers or the push down stack so as to load such entry address into the program counter to cause the readout of the program block. The entry address stored in the push down stack is selectively discarded when it is indicated to be of no future use by an instruction in the program portion contained in the said block that is being executed.

Number oriented processor

Abstract: An MOS/LSI Number Oriented Processor is provided which is intended for number processing applications. The single chip device provides arithmetic, logarithmic and transcendental functions, test and branch capability, internal number storage and input/output capability. The Number Oriented Processor uses ROM library means to store routines for performing the required functions. The desired function is selected from the library by macro instruction means from an external ROM, RAM or microprocessor. The Number Oriented Processor can be used as a stand-alone processor with external ROM/PROM (or RAM) and program counter; or, it can be configured as a peripheral device on the bus of a microprocessor or minicomputer.

Initial program load system

Abstract: PURPOSE: To load the program stored in external memory to RAM without software processing, by outputting the address set to the address additional circuit to the address bus through opening the gate at the application of power supply. CONSTITUTION: Various control processings are made along the program with the CPU 1 having the program counter internally, program and data are stored to RAM 3, and the initial program load loading the program to RAM 3 is stored to the PROM 4. Further, the additional circuit 9 is provided for the address set to the head address of the program stored in the ROM 4, and the output of the circuit 9 is connected to the address bus 1 via the gate circuit 10. Further, the circuit 10 is opened at the application of power supply to output the address set to the circuit 9 to the bus 11, and the program stored in the cassette magnetic tape 6 as external memory is loaded to RAM 3 with the program stored in ROM 4. COPYRIGHT: (C)1980,JPO&Japio

Programmable sequential logic

Abstract: A programmable sequential logic circuit processes data according to a prom containing instructions of different lengths, each instruction composed of one or several words. The sequential logic circuit comprises a memory containing the instructions and data words, an arithmetic and logical processing unit (ALU), and an instruction register for temporarily storing an instruction word read from the memory. An adder is connected to index the contents of address registers by adding the contents of one of a plurality of data registers. A system clock circuit driven by a clock and an operation code in the instruction register to control the operation of the sequential logic circuit. Access to the ALU is through an input multiplexer inputs of which are connected to the output of the memory and the outputs of the data registers and of the address registers. The output of the ALU is connected to an output bus via a circuit having outputs which adopt a high impedance state when they are not enabled. The output bus is also connected to the inputs of the memory and of the data registers. Complete processing of an instruction according to the instruction word temporarily stored in the instruction register is performed in a plurality of phases under the control of the system clock circuit. A first portion of the plurality of phases is devoted to acquisition of one or several data or instruction words, and the second portion is devoted to the execution of an operation by the ALU according to the operation code maintained in the instruction word stored in the instruction register.

Sequence display device

Abstract: PURPOSE:To enable one to monitor a sequence program even though the program is modified by skipping an invalid instruction and displaying a program of the destination address in the case of a jump instruction. CONSTITUTION:When the monitor key of mode key 20a is pressed and the head address is specified by means of the numeric key 20b, the sequence program is read by the program reader 25 from the memory 10. The program reader 25 skips an invalid instruction in the sequence program. For a jump instruction, it writes a program given by the memory address, which is commanded by the destination address, in the buffer memory 26. The content written in the buffer memory 26 is displayed on the CRT.

Data processing unit

Abstract: PURPOSE:To perform sub-routine call, etc, independently of software by detecting inter-area boundaries to generate an interrupt signal when the memory part where data is stored is divided into plural areas and addresses across these areas are designated continuously CONSTITUTION:Memory unit 1 is divided into plural segments A0-A15, and hexadecimal addresses 0000-FFFF are assigned to segments A0-A15 respectively, and bits 0-15 are assigned to program counter 2, and bits 16-19 are assigned to segment register 3 Hardware which generates interrupt on boundaries between two segment areas out of segments A0-A15 is provided with program counter 11 corresponding to counter 2, added register 12, segment register 13 corresponding to register 3, adder 14 and address latch 15, and thus, this hardware is so constituted that boundaries of respective areas can be detected, and an interrupt signal is generated from interrupt signal generation circuit 16

Memory unit for hysteresis of program

Abstract: PURPOSE:To know the hysteresis of a program by recording the contents of a program counter within the word length of the memory going back to the past at every branch establishment.

Microprogram interruption control system

Abstract: PURPOSE: To perform instruction control with neither increase in the number of circuits nor waste of time, by the logic state of interruption request signal lines to part of bits of a program counter and by perform a process with the rest set to a fixed value. CONSTITUTION: The logic state of the n-number interruption request signal lines RQi at the time of interruption is set to fixed bits of program address counter PC by way of switching circuit SW. The remaining bits of counter PC are fixed to a fixed value and therefore when an interruption request is sent to one of signals lines 1 to (n), counter PC is set to an address value equivalent to the interruption request state of them and has a different address. Then, this is used as the head address of an interruption process routine where a branch operation is performed. Consequently, an interruption address circuit attending on an interruption control circuit on an address vector system can be simplified. COPYRIGHT: (C)1979,JPO&Japio

Program control device for small and middle switching systems

Abstract: A data processor for a telecommunication system comprises a program and data memory ME controlled by a block MEV including address registers C1, C2, an address store ACT and an instruction counter US, the memory exchanging information with the components of block MEV and with a set of working registers REG via a reading bus lrl and a writing bus lw; another reading bus lr2 interlinks some of the aforementioned components. An associated execution unit includes an instruction register U divided into two sections MR and UR receiving instruction words from the writing bus, these words consisting of a group of operand bits fed from section UR to a microprogrammed command-signal generator MV and a group of transformation bits fed from section MR to an address store MC. The signal generator MV emits commands for the transfer of addresses from block MEV to memory ME as well as for the readout of data from that memory to an arithmetical unit ALU also receiving data from registers REG, unit ALU being controlled by the contents of store MC; the latter is divided into a plurality of fields all containing the same number of operating instructions (here four) selectable by the transformation bits from register section MR while the field is identified by a bit group received from signal generator MV. Instruction counter US includes two counting registers, P1, P2 connected in parallel between the writing bus lw and the reading bus lrl, the first counting register P1 being stepped by commands from generator MV and having another output which works under the control of that generator into a counting input of the second counting register P2 also having an output connection to the internal bus lr2. Address store ACT includes two data-page registers Y1, Y2 with inputs connected to the writing bus lw and outputs connectable in a predetermined sequence, via a switching network YK, to the internal bus lr2.

Temporal stopping circuit for program counter

Abstract: PURPOSE:To increase the operation speed, by fixing the address storing the program counter with increase of a little hardware, executing the instruction in the same address with arbitrary number of times, and decreasing the number of program steps.