Showing papers on "Residue number system published in 1983"

An improved residue number system digital-to-analog converter

Abstract: A new technique for Residue Number System (RNS) Digital-to-Binary or Digital-to-Analog conversion based on the Chinese Remainder Theorem allows conversion with only one level of ROM and one level of Adders. The ROM's are small (e.g., 256 x 8) and the Adders use standard binary adders. Compared to previous Chinese Remainder Theorem or Mixed-Radix-Conversion Techniques, the new technique offers conversion times which are independent of the number of Residue Number System moduli and conversion times are usually much faster than competative techniques. The new technique also allows for rounding or truncation to fewer bits and sign-detection by simple modifications to the procedure. These modifications yield particularly simple and fast hardware.

Residue Arithmetic and VLSI

Abstract: In the residue number system arithmetic is carried out on each digit individually. There is no carry chain. This locality is of particular interest in VLSI. An evaluation of different implementations of residue arithmetic is carried out, and the effects of reduced feature sizes estimated. At the current state of technology the traditional table lookup method is preferable for a range that requires a maximum modulus that is represented by up to 4 bits, while an array of adders offers the best performance fur 7 or more bits. A combination of adders and tables covers 5 and 6 bits the best. At 0.5 mu m feature size table lookup is competitive only up to 3 bits, These conclusions are based on sample designs in nMOS.

A multiplier with multiple error correction capability

Abstract: This paper presents a technique for increasing the reliability of arithmetic units. An error model is then presented; this model we'll represents the faulty behavior of many arithmetic units. The Residue Number System and its related properties are used in order to obtain a simple architecture (called Reliability Network, R-Net). The main characteristics of the presented technique are a significant reduction in the number of gales and a limited increase of global execution times. The extensive use of combinational logic makes it possible to implement the R-Net almost completely by means of Programmable Logic Arrays (PLA's). Finally, both the intrinsic regularity of the R-Net and its simple internal interconnection scheme make this approach suitable for a practical VLSI implementation.

Sign Detection and Implicit-Explicit Conversion of Numbers in Residue Arithmetic

Abstract: A new method of sign detection is proposed. The advantage of this method is a possibility of simultaneous execution of two operations: residue to mixed-radix conversion of the number magnitude and sign detection in one and the same circuit (implicit-explicit conversion).

Models for VLSI implementation of residue number system arithmetic modules

Abstract: This paper discusses the implementation of RNS arithmetic modules using VLSI technology. The modules are based on the interconnection of read-only memory look-up tables. The paper first outlines a memory model for a single look-up table which allows the selection of the most efficient layout for memories which do not have power of 2 dimensions. The paper then discusses various examples of interconnected memory modules with associated optimizing layout algorithms. Finally, an example is given of the application of one of the modules to a large prime modulus multiplier.

Residue number system holographic truth-table look-up processing: detector threshold setting and probability of error due to amplitude and phase variations.

Abstract: The use of a holographic content-addressable memory system for parallel truth-table look-up digital data processing is analyzed. For binary-coded residue numbers, the operations of 4-, 8-, 12-, and 16-bit addition and multiplication are treated. The minimum probability of error that can be achieved and the corresponding detector threshold settings are determined in each case allowing for the effects of Gaussian distributions in the amplitude and the phase in the recording beams. Resultant probabilities of error for practical conditions are found to be very competitive with those from state-of-the-art nonparallel technologies.

A Residue Number System Implementation of the LMS Algorithm Using Optical Waveguide Circuits

Abstract: A detailed design of a real-time data processor based on the residue number system is presented which uses near-term optical waveguide devices and concepts. The optical computational units consist of cascaded, mask-programmable arrays of total internal reflection electrooptic switches arranged on a LiNbO3 substrate in a serpentine configuration. This paper describes these computational units and then concentrates on the computational and residue-related aspects of the processor. A new scaling algorithm is presented which is based on the Chinese remainder theorem and performs scaling during a single clock period. The least-mean-square adaptive filter algorithm with eight weights is tailored to the optical waveguide residue arithmetic format and requires only three computational stages per iteration. Detailed computer simulations of the processor have verified the design and representative output is included. An envisioned 8 ns clock period corresponds to 2.5 × 109 operations/s ( 2.5 G operations/s) using the equivalent of 23 bit internal precision, which compares favorably to expected rates using established technologies.

An Overflow-Free Residue Multiplier

Abstract: Residue arithmetic is receiving increased attention due to its ability to support very high-speed parallel arithmetic. However, dynamic range overflow remains a serious problem. Contemporary overflow management schemes rely on inefficient scaling algorithms. In this paper, an overflow-inhibiting residue multiplier is architected and tested. The system makes use the popularthree moduliset{2n − 1,2n, 2"+ 1}. Based on 4K high-speed memory technology, a practical 16-bit multiplier can be configured. An error model for the derived residue arithmetic unit is presented and experimentally verified.

On hard errors in RNS architectures

Abstract: The residue number system (RNS) has been shown to be effective in realizing high-speed algorithms and transforms. Due to the modular nature of the numbering system, any hard error can be disastrous. In this work, hard RNS random errors are modeled and experimentally verified.

Sign detection in Non-Redundant Residue Number System with reduced information

Abstract: A necessary and sufficient condition for sign detection in Non-Redundant Residue Number System by reducing the information of a residue digit has been obtained. The function to reduce the information of a residue digit x p corresponding to a modulus m p has been assumed to be periodic with the period length equation, where equation and equation. A sequential method for determining the sign of a number is shown to demonstrate the applicability of the results thus proved.