Showing papers on "Stuck-at fault published in 1968"

Fault Testing and Diagnosis in Combinational Digital Circuits

Abstract: —he problem of designing test schedules for the testing or diagnosis of a small number of nontransient faults in combinational digital circuits (switching networks) is considered in detail. By testing and diagnosis we mean the following: 1) detection of a fault, 2) location of a fault, and 3) location of a fault within the confines of a prescribed package or module. It is shown that minimal test schedules can be readily derived–using procedures already worked out for solving certain problems in pattern recognition and switching theory–under the assumption that the selection of the test inputs in the schedule is independent of the response of the circuit under test. When this assumption is not made, it is shown that much shorter test schedules are sometimes possible, and procedures are offered for obtaining good ones. Finally, the general status of diagnostics for digital circuits is reviewed and evaluated, and specific problems remaining to be solved are described.

Digital Computer Calculation of Internal Fault Currents in a Synchronous Machine

Abstract: A synchronous machine with a fault in its armature winding may be represented by an equivalent circuit in three symmetrical components. The line and neutral terminals of the equivalent circuit are connected to a system network in each sequence. The fault point of the positive sequence is connected to the neutral of the negative sequence, and so forth, representing a single phase- to-ground, or turn-to-turn, fault. Electromotive forces behind the corresponding reactance are introduced in every branch of the positive-sequence network of the faulty machine and an equivalent electromotive force of the system is considered. The resulting network consists of three loops with four electromotive forces. The calculation of the current flow in this network is programmed for solution on the IBM-7090 digital computer.

Fault Tree for Safety

Abstract: : Effective system safety engineering requires a method for examining proposed designs, identifying potential undesirable events, and recommending solutions that will prevent those events from occurring. To accomplish this, the Fault Tree technique was conceived in 1962. Subsequently, Boeing successfully applied the technique to the Minuteman ICBM system. Recent refinement of the technique has permitted its adaptation to dynamic systems such as aircraft. The same desirable features that gained Fault Tree its wide acclaim on Minuteman has been retained in its adaptation to aircraft systems. The Fault Tree process utilizes logic diagrams to portray and analyze potentially hazardous events. As employed by Boeing, this involves the following six steps: (1) Define undesired event, (2) Acquire understanding of system, (3) Construct fault tree, (4) Collect quantitative data, (5) Evaluate fault tree probability, (6) Analyze computer results. Three basic symbols (logic gates) are adequate for diagramming any fault tree. However, additional recently developed symbols can be used to reduce the time and effort required for analysis. In addition, use of a new technique, called 'Importance Sampling' for generating failure occurrences serves to dramatically reduce the amount of computer time required to produce quantitative results. Fault Tree analysis can be applied to virtually any system, design, or procedure with positive results. It fills the need for a quantitative safety analysis capable of extreme detail. In addition, it provides an extremely useful tool in determining the weak points in a design, whether or not numerical analysis is applied.

High-speed fault simulation for UNIVAC 1107 computer system

Abstract: A high-speed logic simulation system of programs with the ability to simulate logic faults has been implemented for the UNIVAC(R) 1107 Computer System. The central simulator program is capable of achieving an average speed of less than one-half microsecond per logical element and has a capacity of up to 10,000 logical components, with a simulated memory of 256 bytes. Among the techniques employed to achieve the speed are (1) logical component “levelizing,” an automatic logic equation ordering method, (2) compiler method of equation evaluation, (3) parallel or simultaneous evaluations of the model, (4) storage of the model equations in main memory storage and (5) for fault simulation, parallel fault perturbations.