Showing papers on "Synchronous Data Flow published in 2004"

Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models

Abstract: As SystemC gains popularity as a modeling language of choice for system-on-chip (SOC) designs, heterogeneous modeling in SystemC and efficient simulation become increasingly important. However, in the current reference implementation, all SystemC models are simulated through a non-deterministic Discrete-Event simulation kernel, which schedules events at run-time. This sometimes results in too many delta cycles hindering the simulation performance of the model. The SystemC language also seems to target this simulation kernel as the target simulation engine. This makes it difficult to express different Models Of Computation naturally in SystemC. In an SOC model, different components may need to be naturally expressible in different Models Of Computations. Some of these components may be amenable to static scheduling based simulation or other pre-simulation optimization techniques. Our goal is to create a simulation framework for heterogeneous SystemC models, to gain efficiency and ease of use within the framework of SystemC reference implementation. In this paper, we focus on Synchronous Data Flow (SDF) models, where the rates of data produced and consumed by a data flow node/block are known a priori. In digital signal processing (DSP) applications where relative sample rates are specified for each DSP component, such models are quite common. Compile time knowledge of these rates allow the use of static scheduling resulting in significant improvement in simulation efficiency. We describe an alternate SystemC kernel that exploits such static scheduling of SDF models. Our experiments show improvement in simulation time over the original models and over the latest efficiency results from [20].

Timing analysis model for network based multiprocessor systems.

Abstract: In this paper an embedded multiprocessor system on top of a network on chip is proposed which is amenable for timing analysis. This multiprocessor system is intended for multimedia application that process data streams. The temporal behavior of applications executed on this multiprocessor system is derived with a Synchronous Data Flow (SDF) graph in which computation, communication, buffer sizes as well as arbitration is modeled. This graph can be transformed in an event graph which is a special case of a Petri net from which properties like the minimal throughput can be derived with results of MaxPlus Linear System Theory [1]. Our main contribution in this paper is an SDF model of the network in which an arbiter is applied which allows the transfer of a possibly varying but bounded number of words per period.

Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models

Abstract: As SystemC gains popularity as a modelling language of choice for system-on-chip (SOC) designs, heterogeneous modelling in SystemC and efficient simulation become increasingly important. However, in the current reference implementation, all SystemC models are simulated through a non-deterministic discrete-event simulation kernel, which schedules events at run-time. This sometimes results in too many delta cycles hindering the simulation performance of the model. The SystemC language also seems to target this simulation kernel as the target simulation engine making it difficult to express different models of computation (MOC) naturally in SystemC. In an SOC model, different components may need to be naturally expressible in different MOCs. Some of these components may be amenable to static scheduling based simulation or other pre-simulation optimization techniques. Our goal is to create a simulation framework for heterogeneous SystemC models, to gain efficiency and ease of use within the framework of SystemC reference implementation. In this work, we focus on synchronous data flow (SDF) models, where the rates of data produced and consumed by a data flow node/block are known a priori. Compile time knowledge of these rates allows the use of static scheduling resulting to significant improvement in simulation efficiency. We propose source level hints to be provided by the model designer to help express SDF more naturally and to make the new simulation kernel execute special functionalities. Our experiments show significant improvement in simulation time over the original models.

Modelling and simulation of guaranteed throughput channels of a hard real-time multiprocessor system

Abstract: Consumers have high expectations about the audio and video quality delivered by media processing devices. Applications running on these media processing devices, like high quality multi-window television and MPEG-video decoders, require a computational performance in the order of 10-100 giga operations per second. Embedded systems are quickly evolving towards heterogeneous multiprocessor systems, which can provide this performance. An important challenge is to build these systems in a way that they exhibit a predictable temporal behavior. This way it can be guaranteed that the applications will meet their deadlines. The objective of the graduation project was to make a simulation model of the multiprocessor system that can be used to derive the timing behavior of an application that is executed on the system. A Synchronous Data Flow (SDF) graph is introduced in which computation as well as communication is expressed. This SDF graph is constructed in such a way that the worst-case arrival times of data can be observed. To simulate the SDF graph a simulator is built which makes it possible to verify the functional as well as the temporal behavior. From the simulation results it can for example be concluded how the performance of the application can be improved. The last objective of the graduation project was to implement a Communication Assist (CA). The CA is a special piece of hardware which is mainly introduced to decouple computation from communication. The CA can be seen as an autonomous DMA with some additional functionality. In this thesis the functionality of the CA is described in more detail and the CA is implemented in such a way that the system exhibits a predictable behavior.

Embedded Context Aware Hardware Component Generation for Dataflow System Exploration

Abstract: Techniques for the rapid deployment and architectural exploration of complex digital signal processing algorithms on embedded processor platforms are gaining popularity. These become significantly more complicated when dedicated hardware components need to be integrated. The models on which such design methodologies and tools are based highlight the system level inflexibility with both pre-designed intellectual property cores and most customized component creation techniques. This paper presents a technique for overcoming these deficiencies using a dataflow model of computation, by allowing flexible circuit architectures to be created that can be optimized as desired, providing increased throughput with no extra resource usage in some situations.

Hardware Synthesis of Synchronous Data Flow Models

Abstract: HARDWARE SYNTHESIS OF SYNCHRONOUS DATA FLOW MODELS