Showing papers on "Synchronous frame published in 1997"
05 Oct 1997
TL;DR: The analysis and design of current regulators for multi-phase AC loads is presented using complex vector notation and several ways of improving its performance are suggested and investigated.
Abstract: The analysis and design of current regulators for multiphase AC loads in AC machines is presented using complex vector notation. The use of complex vector notation provides a way of comparing the performance of controller topologies through their complex vector root locus and complex vector frequency-response functions. Limitations in the performance of the synchronous frame proportional plus integral current regulator are outlined and several ways of improving its performance are suggested and investigated.
335 citations
23 Feb 1997
TL;DR: In this paper, a synchronous frame controller for a single-phase PWM inverter with an LC output filter is presented, where the filter capacitor current and the filter voltage are identically 90/spl deg/out of phase.
Abstract: A synchronous frame controller for a single-phase PWM inverter with an LC output filter is presented. These types of inverters are often used in uninterruptible power supplies (UPS) where a sinewave output voltage is to be maintained. The advantages of a synchronous frame regulator are well known in three-phase controllers where regulated AC variables (voltage, current, flux) are "-rotated" into a frame synchronous to the fundamental output frequency where they appear as DC vector quantities. Such a controller can regulate the steady-state errors of the corresponding DC quantities to zero. While the familiar dq transformation is not applicable in a single-phase system, a frame synchronous to the output fundamental can be formed by recognizing that the filter capacitor current and the filter capacitor voltage are identically 90/spl deg/ out of phase. Thus, orthogonal quantities much like dq components exist, and can be used to create a rotating frame where a composite reference vector can be summed with a similar measured vector. Simulations of a synchronous controller and a conventional state-feedback cascaded controller are presented and compared. Preliminary experimental results are also presented.
52 citations
Patent•
18 Dec 1997TL;DR: In this article, the phase alignment of a plurality of temporal frames, such as synchronous optical network (SONET) frames, includes a phase locked loop 6 coupled to lock the phase of the first frame, a first frame device 8a capable of receiving the first frames and coupled to provide a synchronous frame frequency to the phase-locked loop 6, subsequent frame devices 8b... 8n capable of sending frames subsequent to the first-frame, and a drop clock device 22 coupled to the subsequent-frame device 8b, 8n to set the phases of
Abstract: A frequency and phase locking apparatus for a phase alignment of a plurality of temporal frames, such as synchronous optical network (SONET) frames, includes a phase locked loop 6 coupled to lock the phase of the first frame, a first frame device 8a capable of receiving the first frame and coupled to provide a synchronous frame frequency to the phase locked loop 6, subsequent frame devices 8b . . . 8n capable of receiving frames subsequent to the first frame, and a drop clock device 22 coupled to the subsequent frame devices 8b . . . 8n to set the phases of the subsequent frames in alignment with the phase of the first frame.
4 citations
Patent•
27 Nov 1997
TL;DR: In this paper, the converter comprises a memory (SRAM) having first and second ports, a first port management circuit (SPM) connected to the first port, to an incoming synchronous multiplex line (ME) and to an outgoing synchronous multiples line (MS), and an APM connecting to the second port, via an FIFO type packet memory (M) and an outgoing asynchronous link (LS).
Abstract: The converter comprises a memory (SRAM) having first and second ports, a first port management circuit (SPM) connected to the first port, to an incoming synchronous multiplex line (ME) and to an outgoing synchronous multiples line (MS), and a second port management circuit (APM) connected to the second port, to an incoming asynchronous link (LE) via an FIFO type packet memory (M) and to an outgoing asynchronous link (LS) An external command (MF) applied to the port management circuits selects the converter operating mode; in a first mode (M32) each time slot of a frame of a synchronous multiplexed signal is assigned to one communication channel and in a second mode (M1) all the time slots of a synchronous frame are assigned to one channel
2 citations
TL;DR: In this paper, a new adaptive vector control scheme for inverter-fed induction motors is presented, which adaptively identifies motor parameters varying dynamically with temperature and magnetic saturation and determines critical parameters of vector control system.
Abstract: This paper presents a new adaptive vector control scheme for inverter-fed induction motors. The scheme proposes new system structure consisting of two subsystems for adaptive vector control, a vector control system realized on synchronous frame and a parameter identification system on stationary frame. Proposed adaptive identification system can perform in different rate from that of the control system, which adaptively identifies motor parameters varying dynamically with temperature and magnetic saturation and determines critical parameters of vector control system. The high performance of the proposed scheme verified by a real drive system is also shown.