Showing papers on "System bus published in 2022"

A Review and Analysis of Attack Vectors on MIL-STD-1553 Communication Bus

Abstract: MIL-STD-1553 has been used for the past four decades by the military as a standardized, reliable, and fault-tolerant communication bus to provide connectivity between different embedded components in mission-critical military vehicles. The bus was designed with a great focus on reliability, responsiveness, and fault tolerance. However, its security aspects were an afterthought. Indeed, in the early 1970s, the notion of cyberattacks was not ubiquitous as it is today. Attacking computerized systems located at very high altitudes was an inconceivable scenario for many people, including security engineers. With current developments in cybersecurity and telecommunication networks, the security analysis of the MIL-STD-1553 bus reveals that the system is not immune from cyberattacks. The bus is vulnerable to many attacks that could seriously damage the entire system. Rebuilding the security of MIL-STD-1553 from scratch is cost prohibitive and a very complex, not scalable, and inflexible approach. A common alternative to embedding security to the existing system is the development of an intrusion detection system that can be added to the MIL-STD-1553 bus with minimal cost. In this article, we review and discuss some possible attack vectors on the MIL-STD-1553 bus. Then, we analyze the risk and consequences of each attack vector on a fighter jet. This review and analysis will provide security engineers with a holistic overview of possible attacks and their related risk on MIL-STD-1553 to better design an effective intrusion detection system.

Scalable and Configurable Electrical Interface Board for Bus System Development of Different CubeSat Platforms

Abstract: A flight-proven electrical bus system for the 1U CubeSat platform was designed in the BIRDS satellite program at the Kyushu Institute of Technology. The bus utilizes a backplane board as the mechanical and electrical interface between the subsystems and the payloads. The electrical routes on the backplane are configured by software using a complex programmable logic device (CPLD). It allows for reusability in multiple CubeSat projects while lowering costs and development time; as a result, resources can be directed toward developing the mission payloads. Lastly, it provides more time for integration and system-level verification, which are critical for a reliable and successful mission. The current trend of CubeSat launches is focused on 3U and 6U platforms due to their capability to accommodate multiple and complex payloads. Hence, a demonstration of the electrical bus system to adapt to larger platforms is necessary. This study demonstrates the configurable electrical interface board’s scalability in two cases: the capability to accommodate (1) multiple missions and (2) complex payload requirements. In the first case, a 3U-size configurable backplane prototype was designed to handle 13 mission payloads. Four CPLDs were used to manage the limited number of digital interfaces between the existing bus system and the mission payloads. The measured transmission delay was up to 20 ns, which is acceptable for simple serial communications such as UART and SPI. Furthermore, the measured energy consumption of the backplane per ISS orbit was only 28 mWh. Lastly, the designed backplane was proven to be highly reliable as no bit errors were detected throughout the functionality tests. In the second case, a configurable backplane was implemented in a 6U CubeSat with complex payload requirements compared to the 1U CubeSat platform. The CubeSat was deployed in ISS orbit, and the initial on-orbit results indicated that the designed backplane supported missions without issues.

Design of Aeronautical Digital Video and Communication Bus Processing System

Abstract: With the development of avionics systems, Avionics Digital Video Bus (ARINC 818) and Digital Information Transmission System (Arinc429) have become a new generation of aviation video transmission and communication bus standard respectively. Aiming at the characteristics of ARINC 818 and Arinc429, an aeronautical digital video and communication bus processing system is designed. First, the ARINC 818 aviation video transmission bus and the Arinc429 communication bus standard are introduced. Then, the design principles of the aeronautical digital video and communication bus processing system are described according to this standard, and the design scheme of each system component is introduced in detail. Finally, build a hardware test platform for testing and verification. The system development follows an integrated and modular design, with the Application Processing Unit (APU) main processor and Field Programmable Gate Array (FPGA) as the core, which realizes the superposition of 1-channel input ARINC 818 video with internally generated characters, and then outputs 1-channel ARINC 818 to the function displayed on the display. At the same time, it supports 7-channel Electronic Industries Association-422 (EIA-422) and 4-channel Arinc429 bus communication. In addition, the system supports the processing of 22 input discrete quantities and 7 input analog quantities. The design has been successfully used in a certain type of aircraft display control management system.

Design of 1553B bus interface module based on NIOS II

Abstract: The MIL-STD-1553B bus (1553B for short) is a centralized time-sharing serial bus. Among the current military data buses, the 1553B bus is the most mature and widely used data bus. This paper expounds a design method of 1553B bus communication system with CPCI bus interface. The host system communicates with 1533B interface module through CPCI bus interface. The core structure is FPGA(EP2C35F672I8N), CPCI bus interface bridge chip (PCI9054) and 1553B bus controller (61580), The design, debugging and testing of 1553B bus interface module are realized by using NIOS II soft core processor.

A Universal Bus Management Method for Multi-Computer Multi-Bus System

Abstract: High reliable computer systems mainly adopt the redundant backup methods to construct complex multi-computer multi-bus fault-tolerant systems. How to design the bus management logic is a key problem for these kinds of systems. In this paper, a universal bus management method is introduced to improve the system's fault tolerance ability. The method adopts the global optimization strategy, by scoring all of the possible bus management statuses and finding out the best one. The score of each bus management status is composed by 3 parts: bus score, computer score and interface chip score. There are several adjustable parameters in the scoring logic. By adjusting the parameters, different bus management strategy can be generated. So the proposed method can be widely used. The validity of the bus management method proposed is verified by simulations and experiments on the GNC system of a spacecraft.

A Novel Bus Controller For Advanced Microcontroller Bus Architecture

Abstract: In a typical SoC, communication between the sub-blocks is very crucial which dictates the entire SoC performance. As many of the resources are shared in a SoC, the protocol used for communication should have some characteristics which would help in increasing the overall performance of the SoC. AMBA (Advanced Microcontroller Bus Architecture) is one such protocol which characterizes the specifications of the communication bus. The special feature of the bus is that the design, implementation and testing of the sub-blocks in a SoC using AMBA is technology independent. In this paper, a novel bus controller for AMBA is implemented by employing two methodologies namely, Data Flipping and Instruction Decoding. Modelsim from Mentor Graphics and NC launch from Cadence are used for functional simulation. Genus from Cadence is used for synthesis at 180nm. Area, power and timing reports are analyzed after synthesis.

The Configuration and Verification Analysis of AMBA-Based AHB2APB Bridge

Abstract: To strengthen the IP core’s reusability, AMBA is the on-chip bus architecture used widely for interconnection standards of SOC. In AMBA Architecture, Advanced High-performance Bus is connected to an ARM control unit, memory interface, digital signal processing(DSP) and an Advanced peripheral bus used to connect to a timer, UART, keypad, and PIO. A bridge is a standard bus-to-bus interface that helps to build the communication gap between AHB and APB. Another importance of constructing a bridge is to avoid data loss when data transfer is initiated. So keeping this in mind, the upgradation in technology, tools and methodologies has made the need for advancement in the verification environment. In this paper, presents the design and verification of the AMBA-based AHB2APB Bridge. The verification environment is developed in the Questa-sim simulator. To verify the functional and code coverage multiple test cases like Increment, Wrap Read and write cycles with different bit sizes of 4,8,16 bits are done, and 100 percent Functional & 97 percent code coverage are achieved.

A Bus Controller Software Design Method for 1553B Communication System

Abstract: This text puts forward a design scheme of 1553B bus protocol controller through the analysis of MIL-STD-1553B protocol. Introduced in detail the function analysis of the protocol controller, planning the overall design plan and port description, module task division and writing code logic implementation, building a test platform for experimental verification and debugging, including the bus interface chip test system, and choosing TMS320LF2407 as the main processor , The test includes the verification of the main processor's spontaneous transmission and reception, and the addition of the RS232 serial port debugging process improves the intuitiveness of the test data and improves the efficiency by 6.5%.

Improvement of Automotive Sensors by Migrating AUTOSAR End-to-End Communication Protection Library into Hardware

Abstract: This paper explores new methods to increase the level of safety of data transfer between sensors and electronic control units (ECUs) in automotive communication. A new model of basic sensors to be used in automotive electronics is proposed. This model contains hardware modules that implement the end-to-end communication protection (E2E) mechanism, as defined by the Automotive Open System Architecture (AUTOSAR) standard. By adding this feature inside the sensors, it is possible that, in addition to increasing the safety level, these sensors can be directly connected to the network ECUs via standard communication buses (e.g., Local Interconnect Network (LIN), Controller Area Network (CAN), Flexray, etc.). This paper describes the model, design, and mapping (in a Field Programmable Gate Array device (FPGA)) of the hardware E2E module capable of generating the Cyclic Redundancy Code (CRC) and counter signal for a customized message. This message represents the output of the new sensor E2E module used in a safety communication as requested by the automotive E2E standard. The model is validated also by comparing the data output of the E2E hardware with the data output of the AUTOSAR software E2E library. Finally, future needs and directions are suggested in this area.

A Bus System with Elevated Bus Stops

Abstract: The requirements and desires of the passengers themselves were given first priority in designing the new bus system. The bus system consists of not only the vehicle but also elevated bus stops. The wide doors, operated by a photoelectric cell, are fitted with sensor-type edging to prevent passengers from being hurt by the door. Halmstad made the decision to try the bus system, and before it was put into operation in November 1979, all drivers were trained in the new system. The elevated bus system makes a tremendous difference to persons suffering from decreasing physical and mental ability due to the aging process as well as to disabled persons. The importance of public transportation to the elderly is obvious. The quality of the public bus service can have a major impact on the quality of an elderly person’s life.

Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus

Abstract: Accessing embedded test and monitoring circuitry (the so-called embedded instruments) in in-field products can reduce maintenance and diagnostics costs. Performing such access can be facilitated when done over an internal system bus, due to that it might be faster and less cumbersome to reach a system processor (on an in-field product) over a network interface, compared with the effort and speed of gaining access to a test interface on the same product. Enabling such access might require that, at the component level, the embedded instruments in a system-on-chip (SoC) become accessible both from a chip interface and from an on-chip processor over a system bus. Although this reuse of embedded instruments can be achieved by already existing standards, such as IEEE 1687, the system bus might become a scalability bottleneck when the number of instruments that are to be reused increases. In this paper, we propose two solutions that address the scalability in this type of reuse while maintaining compatibility with IEEE 1687 tools. We also discuss the trade-offs associated with each approach and present timing analyses that by considering system parameters such as clock rates determine how the correct operation can be guaranteed. To validate the proposed solutions, we have implemented them on an FPGA using AXI as system bus, and have used standard IEEE 1687 tools to access the instruments. We present some details of the implementation to highlight practical issues such as clock domain crossing, as well as how the presented timing analyses can be used to adjust design parameters.

LIN Bus Based Touchpad System for Smart Vehicle Cabin

Abstract: The concept of smart cabin is to offer better safety, comfort and ride the experience for vehicle drivers. In order to make this concept realize better, an array of advanced human interface (HMI) is always needed. In general, the HMI will transmit control signal either through the CAN bus, LIN bus or both to control end devices or instrumentation. This paper presents a LIN bus touchpad system (LBTS), which enables safe and efficient devices (headlight, taillight and cooling fan) access as well as control of their operating parameters.In this LBTS, the touch pad signal processing system is designed with a LIN bus based controller CS8975 developed by the company ISSI we collaborated. A high performance STM32 Nucleo-64 board is used to realize the LIN master node, dealing with the control of the LIN message sequence. With this proposed LBTS, the interior design for the smart human-centric cabin can be more flexible and innovative.

Design of multi-protocol conversion module

Abstract: In view of the communication difficulties of CNC machine tools with only RS232 and RS485 interfaces in industry, this paper studies DNC technology and multi-protocol conversion technology, proposes to use CAN bus to build DNC system, establish multi-protocol conversion module communication model, and build software and hardware platform based on STM32F103VCT6 MCU. The CAN bus protocol, RS232 bus protocol and RS485 bus protocol CAN be converted to each other. The experimental results verify the accuracy and reliability of the multi-protocol conversion module, realize the two-way transmission of data, and solve the problem of communication difficulties between different protocols.

Intelligent Accidental Detection and Prevention System for Car using Can FD Protocol

Abstract: Controller Area Network with Flexible Data Rate (CAN FD) is a vehicle bus standard protocol designed especially for automotive application. By using CAN FD Bus protocol, ECUs (Electronic control units) of vehicles can communicate with each other. It is a high speed, bandwidth efficient network. In order to reduce point to point wiring harness in vehicle automation, CAN FD is suggested as a means for data communication within the vehicle environment. The benefits of CAN FD bus based network over traditional point to point schemes will offer increased flexibility and expandability for future technology insertions units. We have designed five nodes, 4-sensor nodes and 1-Bus monitor nodes. Sensor nodes and Bus monitor nodes are communicating with each other through CAN FD Bus. Bus monitor node collects all messages present on the CAN FD Bus and transmits to the PC by using the UART interface. The CAN FD monitor window is designed using Visual Studio.net which allows the time oriented buffering of CAN FD messages and visualization of the BUS data at the package level.

Secure Communication between Arduinos using Controller Area Network(CAN) Bus

Abstract: Present-day vehicles have numerous Electronic Control Units (ECUs) and they communicate with each other over a network known as the Controller Area Network(CAN) bus. In this way, the CAN bus is a fundamental component of intra-vehicle communication. The CAN bus was designed without focusing on communication security and in this way it is vulnerable to many cyber attacks. As the vehicles are always connected to the Internet, the CAN bus is remotely accessible and could be hacked. To secure the communication between ECUs and defend against these cyber attacks, we apply a Hash Message Authentication Code(HMAC) to automotive data and demonstrate the CAN bus communication between two ECUs using Arduino UNO and MCP2515 CAN bus module.

High-Speed SPI Bus Host Controller for Embedded Systems

Abstract: The article focuses on the consideration of the two-level embedded control systems construction based on the SPI bus, in which the Wi-Fi module in the master mode acts as a component of the upper level, effectively implements extended HMI functionality and CNC program buffering. The expediency and possibility of such control systems is substantiated, a practical solution option is offered. The clock frequency of 40MHz and word bit rate of 16 bits was defined as optimal. The advantages of composite decryption of system signals and multiplexing of clock signals are considered. The software model of information exchange is given. Block transaction mode DMA hardware support has been developed. The main differences of the offered high-speed SPI bus from standard decisions, perspective directions of the host controller realization and technical and economic advantages of its use are noted.

Design and Analysis of Reduced-Connection Multiple Bus Systems: A Probabilistic Approach.

Abstract: In the dissertation we have proposed the first systematic and formal approach to reduce connectivity of general purpose multiple bus systems. The approach is based on a probabilistic technique. The hypothesis on which this dissertation is based stipulates that bus connectivity in multiple bus systems can be much reduced by removing connections which are only needed for highly improbable request patterns. With this approach, performance comparable to that of the original multiple bus system could be achieved while significantly reducing memory bus connectivity. The new architecture thus obtained (Probabilistically load reduced connection multiple bus system, or PRMB in short) might have different possible configurations each possibly with a different bus connectivity cost. We have studied the possible relationship among different possible configurations of PRMB systems and proposed an algorithm that determines the one with minimum memory-bus connectivity cost for a given performance level. Our analysis results strongly supported our hypothesis. The queuing problem for PRMB systems is a complicated one because of its unique modeling requirements. An interesting and innovative modification of aggregation technique has been developed to solve queuing problem taking into account bus contention in PRMB system. We have utilized the proposed approximate technique to determine the system throughput. We have also simulated the queuing networks without applying any approximations. Comparison of analytical results with simulation data indicated that our approximate method could accurately be used to model such queuing networks. The results indicated that our hypothesis is valid when queues are utilized. We have proposed another variant of the PRMB system which attempts to reduce the connectivity cost from both the processor side and the memory side. Our results indicated that, except under certain specific conditions, this variant of PRMB system did not offer any cost improvement over the original version. It is quite possible that PRMB system is so efficient that further reduction may not be possible without sacrificing some performance. The technique presented in this dissertation is of very general nature and could possibly be applied to other types of networks as well.

SV1DUR: A Real-Time MIL-STD-1553 Bus Simulator with Flight Subsystems for Cyber-Attack Modeling and Assessments

Abstract: MIL-STD-1553 is a widely used communications protocol in the military aircraft for many North Atlantic Treaty Organization (NATO) countries. The Department of Defence designed this protocol before the advent of cybersecurity, making it an easy target for malicious actors. Researchers have been working to find affordable ways to secure the communications bus using non-invasive means such as the addition of an Intrusion Detection System (IDS). Many of the researched IDS systems are calibrated using small-scale datasets which do not provide sufficient training data for complex IDS systems or use proprietary hardware systems that restrict access to researchers with strong financial incentive to perform this research. Other attempts to address this accessibility gap have produced slow and inaccurate simulations at both the bus level, and the terminal level. We propose a real-time MIL-STD-1553 bus simulator. The proposed simulator will be capable of replicating correct timing for message passing and response as well as supplying an extensible framework for building in custom attacks, schedules, and terminals.

Design of Electric Vehicle Control System Based on CAN Bus

Abstract: The control system of electric vehicle is designed by using CAN2.0B communication protocol of CAN bus technology. Distributed control system is adopted. PC/104 computer + CAN communication card is selected as the upper computer, and the key nodes of driving motor are composed of DSP chip TMS320LF2407 Experiments show that the system has high communication reliability and can ensure the safety of vehicles in real time.

Security verification of 1553B bus components used in aerospace

Abstract: 1553B bus is a network interface that manages the bottom communication and control of the hardware system. It is widely used in the aerospace field because of its high reliability, high noise tolerance and flexible connection between devices. However, the basic security protection mechanism wasn’t considered in this bus design. A security verification platform to verify the existence of the security vulnerability was design in this paper, based on which some typical 1553B bus components are verified. The results show that the key node vulnerabilities of 1553B bus system can be exploited, which will affect data transmission and lead to system security failure.

GALS Clocking and Shared Interconnect for Large Scale SFQ Systems

Abstract: A globally asynchronous, locally synchronous clocking scheme for large scale single flux quantum systems is described in this chapter. In this scheme, the width of each data bus is extended to carry the corresponding clock signal. This signal activates the distribution of the clock signals within the receiving block. Based on this approach for intra-chip interconnect within SFQ systems, a configurable shared bus is also proposed. The data are attached to a tag, and a resulting data packet is sent to the shared bus. This packet is received by each block, but only processed if the tag matches the block identifier. By avoiding expensive comparators and multiplexers, the overhead of the global bus connection is reduced. The proposed approaches exploit the pulse-based nature and ambiguity of clock and data in SFQ technology—the data packet propagating through the interconnect carries a local clock signal.

Design and Implementation of Electronic Communication System Bus Based on DSP

Abstract: Aiming at the defects of current electronic bus data communication system in transmission rate, real-time performance and anti-interference ability, a bus data communication system based on DSP is proposed. We mainly introduce the new characteristics of TMS320F2812 DSP controller, and make communication between CAN modules through this chip. Then, combined with the actual design and implementation of software and hardware, the system test platform is established, and the corresponding programming and transplantation process are provided. The system debugging results show that the bus system has high reliability and speed of data conversion, simple hardware circuit design and software programming, which can effectively transmit and store the acquired data.

Design of MIL-1394 bus simulation card

Abstract: In the development of MIL-1394 (Military 1394) products, users need to buy simulation equipment withdifferent functions when building simulation network. It is not only expensive,but also a burden for users to be familiar with the configuration mode and application interface of different equipment. Combined with IEEE-1394B (Institute of Electronic Engineers 1394b) and SAE AS5643 (Society of Automotive Engineers Aerospace Standard 5643) protocols, this paper designs a Mil-1394 bus four node simulation card, which is used to simulate the functions of CC (Control Computer) and RN (Remote Node) nodes in 1394 bus. It has four independent 1394 nodes and supports bus data recording error injection and other functions to realize the data transmission of 1394 bus network.

A Novel Bus Arbiter Based on Group Decision Algorithm

Abstract: The arbiter is an essential component of the system-on-chip (SoC), network-on-chip (NoC), and classic interconnect bus, which is located in the critical path of these systems. The multi-master interconnect system has various performance limitations, but an effective arbiter can handle the contention caused by more than one master requesting access at once, preventing system performance degradation. For the advanced microcontroller bus architecture (AMBA), particularly for the advanced high-performance bus (AHB) frequently utilized in SoC design, the group decision (GD) bus arbiter is proposed. To combine the benefits of various arbitration systems and create a new priority sequence, the Borda concept is introduced. In contrast to the fixed priority (FP) bus, the frequently requested response from the masters can be quickly satisfied in the GD bus. In a multi-master SoC, our method can reduce the waiting time of masters that frequently access the bus by 50% in comparison to the round-robin (RR) bus, thus preventing the hunger issues. Moreover, our system uses VCS and Verdi for co-simulation, and utilizes the Design Compiler for synthesis. The results of the experiment show that a GD arbiter of 16 masters can reduce the waiting time to a certain extent and achieve 12.5% of the bus occupancy rate of commonly used masters compared to the bus with FP or RR arbiter.

Design of A Novel 1553B Data Communication Board Based on DSP and Integrated 1553B Terminal

Abstract: In order to make the communication cables in airborne equipment not as complicated, large and heavy as before, the MIL-STD-1553B standard was released in the 1970s, thus reducing aircraft weight. Application of 1553B bus is becoming wider and wider. In recent years, UAV is a new force in modern battlefields and local conflicts. At the same time, the 1553B bus is prevalent in the domain of UAV for communication between different devices. A novel 1553B data communication board based on DSP and integrated 1553B terminal is designed in this paper. The principle of 1553B bus is introduced at first. And then it presents the hardware design as well as the software design. In the end, the conclusion part summarizes its applications. Undoubtedly, the 1553B board designed in this paper is convenient to be integrated to the whole system, providing a real-time, reliable and flexible communication solution for UAV.