Showing papers on "Universal memory published in 1988"
01 Jan 1988
TL;DR: The device is a high-density nonvolatile flash memory optimezed for microprocessor-controlled reporgramming capability and has a 200ms electrical erase time, and a 100p/byte program time.
Abstract: ADVANCES in TUNNEL OXIDES have made it possible to develop a 256Kb double-poly, single-transistor, electrically erasable, programmable flash memory. The device is a high-density nonvolatile flash memory optimezed for microprocessor-controlled reporgramming capability. Using advanced CMOS 1 . 5 m technology, a 192mil square, 32,768 x 8b device has been designed with a 6pm x 6m cell; F i g r e l. The memory has a l l 0 n s access time with a 200ms electrical erase time, and a 100p/byte program time, Figure 2. Using CMOS inputs, dissipation is 150mW in the active state and 0.50mW in the standby mode.
66 citations
Patent•
28 Oct 1988TL;DR: In this paper, a method and apparatus for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next.
Abstract: A method and apparatus is disclosed for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next. A faster cycle type (e.g. page mode or static column) can thereby be employed in the Dynamic Random Access Memory (DRAM) memory by eliminating the DRAM precharge and RAS address portions of the cycle.
37 citations
16 May 1988
TL;DR: A novel memory circuit, the transparent-refresh DRAM (TReD), is proposed to make a dynamic random-access memory (DRAM) virtually refresh-free, and a test device is successfully fabricated.
Abstract: A novel memory circuit, the transparent-refresh DRAM (TReD), is proposed to make a dynamic random-access memory (DRAM) virtually refresh-free, and a test device is successfully fabricated. The TReD uses dual-port dynamic RAM cells, one port of which is assigned for a refresh operation and the other port is assigned for a normal read/write operation. Using the configuration, users of the RAM are freed from a cumbersome refresh control without access-time degradation. The TReD cell size is about 1/2.5 of a 4-transistor SRAM (static RAM) cell, so that it can provide very-high-density RAM macros, which is functionally static. As a dual-port memory, the proposed dual-port DRAM cell size is 1/5 of the dual-port SRAM cell, and is suitable for large-scale dual-port memory macros in ASIC (application-specific integrated circuit) environments. >
34 citations