The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms. >

CORDIC-based VLSI architectures for digital signal processing

A detailed analysis of the quantization error encountered in the CORDIC (coordinate rotation digital computer) algorithm is presented. Two types of quantization error are examined: an approximation error due to the quantized representation of rotation angles, and a rounding error due to the finite precision representation in both fixed-point and floating-point arithmetic. Tight error bounds for these two types of error are derived. The rounding error due to a scaling (normalization) operation in the CORDIC algorithm is also discussed. An expression for overall quantization error is derived, and several simulation examples are presented. >

The quantization effects of the CORDIC algorithm

An automatic interface layout generator for database systems is disclosed herein. The automatic generator includes a specification tool for specifying a set of block descriptions representative of specified portions of a database. A block layout generator produces interface objects to be included within an interface of the database, wherein each of the interface objects corresponds to one of the block descriptions and includes a plurality of layout fields. A layout quality parameter is determined for each of the interface objects based on arrangement of the layout fields within the interface objects. A block placement generator arranges sets of the interface objects into block configurations within the interface. A placement quality parameter for each of the block configurations is derived based on a set of block placement rules and on the layout quality parameters, and a final block configuration is selected by comparing the placement quality parameters corresponding to particular block configurations.

Automatic interface layout generator for database systems

The coordinate rotation digital computer (CORDIC) algorithm is used in numerous special-purpose systems for real-time signal processing applications. An analysis of fixed-point CORDIC in the Y-reduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. The authors describe two approaches for tackling the numerical accuracy problem. The first approach builds on a fixed-point CORDIC unit and eliminates the problem by including additional hardware for normalization. A method for integrating the normalization operation with the CORDIC iterations for efficient implementation in O(n/sup 1.5/) hardware is provided. The second solution to the accuracy problem is to use a floating-point CORDIC unit but reduce the implementation complexity by using a hybrid architecture. Arguments to support the use of such an architecture in certain special-purpose arrays are presented. >

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Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors

The authors present a VLSI CORDIC processor which is obtained using the hierarchical and interactive design methodology on which the DELFT VLSI synthesis is built. They also present an optimized (floating-point) CORDIC algorithm, the hierarchical mapping of this algorithm on a floating-point architecture, the design method, the layout, the chip, and its performance. Algorithm, architecture, and layout are parameterized with respect to the accuracy of rotation angles and vectors. The CORDIC chip is a pipeline that performs 10/sup 7/ plane rotations/s and is mounted in a 144-pin package. The vector entries are 21 bit floating-point numbers (16-bit mantissa and 5 bit exponent in twos complement). >

An optimal floating-point pipeline CMOS CORDIC processor

The authors describe the design and implementation of an algorithm and a processor which can be used to accelerate computations in which large amounts of rotations (circular as well as hyperbolic) are involved. The processor is a low-cost high-throughput VLSI implementation of the algorithm. With 10/sup 7/ rotations per second, many real-time and interaction-time applications in scientific computation become feasible. The required storage and/or silicon area is low and the execution time is independent of the particular operation performed. Another feature of this CORDIC design is its pipelined architecture and floating point extension. It is angle-pipelinable at the bit-level and has an execution time which is independent of any possible operation that can be executed. >

Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing

A number of high-speed multiprocessor applications of a fast custom VLSI floating-point pipeline CORDIC processor are presented. The applications are concerned with speech processing, matrix arithmetic, antenna array processing, and computer graphics. The applications are designed using an interactive high-level functional design environment for multiprocessor systems and are implemented on a testbed for high-speed parallel processor arrays. >

The synthesis and implementation of signal processing applications specific VLSI CORDIC arrays

A number of high-speed multiprocessor applications of a fast custom VLSI floating-point pipeline CORDIC processor are presented. The applications are concerned with speech processing, matrix arithmetic, antenna array processing, and computer graphics. The applications are designed using an interactive high-level functional design environment for multiprocessor systems and are implemented on a test bed for high-speed parallel processor arrays. >

Real time application of the floating point pipeline CORDIC processor in massive-parallel pipelined DSP algorithms

A novel approach and system for graph-oriented layout compaction for large symbolic layout designs is presented. Hierarchical compaction is performed by generating geometrical interfaces for compacted subcells which are used as rigid nodes in graphs at higher hierarchical levels. Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in the graphs, which requires an iterative graph-generation/compaction scheme. >

A.A.J. de Lange

Papers

An optimal floating-point pipeline CMOS CORDIC processor

Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing

The synthesis and implementation of signal processing applications specific VLSI CORDIC arrays

Real time application of the floating point pipeline CORDIC processor in massive-parallel pipelined DSP algorithms

A hierarchical constraint graph generation and compaction system for symbolic layout