By means of tables, characters, and the like displayed on the screen of a CRT monitor, a functional diagram editor element can generate, on the screen of the CRT monitor, a functional diagram for representing the operation of a logic circuit. A functional diagram check element detects the presence or absence of a contradiction in the generated functional diagram. Furthermore, a functional simulation element can perform the functional verification of the functional diagram free from contradiction. A hardware-description-language conversion element can generate a hardware description language from the functional diagram in which the circuit operation has undergone error correction. A logic synthesis element can generate netlist information from said hardware description language.

Apparatus and method of supporting functional design of logic circuit and apparatus and method of verifying functional design of logic circuit

Overconstraints in a system, such as an electrical circuit layout, are identified using port abstraction graphs. Intercell pitchmatching constraints are represented by meta-edges between cells. Classes of edges which can be represented by a support edge are created, and the value of the class edges are increased to the value of the support edge. The edge values are updated in the graphs, and the redundant edges eliminated. Overconstraints are identified as positive cycles in the graphs, and a database of the layout is annotated and graphically displayed. The graphical display responds to user inputs to manipulate the display of the relations between constraints. The use of the port abstraction graphs also reduces the number of equations that need to be solved to compact the layout.

Identifying overconstraints using port abstraction graphs

A new hierarchy-preserving hierarchical compactor which can be used with either 1-D or 2-D leafcell compaction techniques has been developed. The compactor is applicable to hierarchical layouts which consist of a number of arrays of identical cells. The hierarchy is maintained throughout the compaction process so that all the instances of a subarray of identical cells have the same shape after compaction. A hierarchical compactor based on the suggested simplified graph model has been developed and experimental results on several benchmark examples showed that the proposed method was satisfactory. >

A new hierarchical layout compactor using simplified graph models

Describes concepts, design and implementation of a Coordinate Rotation Digital Computer (CORDIC) processor element that can be used in processor arrays for high-speed processing. The processor is intended to achieve maximal throughput m-matrix computations. It is a systolic processor that performs plane rotations in two different coordinate systems. >

An application specific IC for digital signal processing: the floating point pipeline CORDIC processor

We propose a new efficient constraint generation technique for 2-D mask compaction based on Branch-and-Bound Optimization (BBO). To assure separation in X and Y between rectangles in a layout, we generate the so called "diagonal" constraints in addition to the usual simple constraints in the X and Y directions. A diagonal constraint consist of two constraints, one in each dimension. Our method determines areas around the rectangles beyond which the diagonal (and the simple) constraints need not be generated, producing thus a nearly irredundant system of constraints. During BBO, the diagonal constraints are treated as dual constraints, in which case, one of the two component constraints of the dual can be deactivated. When a such constraint is deactivated, few additional constraints must be be added to assure a legal layout. The overall performance is still considerably improved, because there are fewer dual constraints. Proofs of sufficiency are based on a novel characterization of the 2-D constraint structure.

Efficient generation of diagonal constraints for 2-D mask compaction

A novel approach and system for graph-oriented layout compaction for large symbolic layout designs is presented. Hierarchical compaction is performed by generating geometrical interfaces for compacted subcells which are used as rigid nodes in graphs at higher hierarchical levels. Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in the graphs, which requires an iterative graph-generation/compaction scheme. >

J.F. Vink

Papers

A hierarchical constraint graph generation and compaction system for symbolic layout