We explore the effect of high-κ dielectric seed layer and overlayer on carrier transport in epitaxial graphene. We introduce a novel seeding technique for depositing dielectrics by atomic layer dep...

Enhanced Transport and Transistor Performance with Oxide Seeded High-κ Gate Dielectrics on Wafer-Scale Epitaxial Graphene

A compact physics-based ambipolar-virtual-source (AVS) model is presented that describes carrier transport in both unipolar and ambipolar regimes in quasi-ballistic graphene field-effect transistors (GFETs). The transport model incorporates two separate virtual sources for electrons and holes and is supplemented by a self-consistent channel-charge-partitioning model valid from drift-diffusive to ballistic transport conditions. The model comprehends the asymmetry introduced by different contact resistances for electrons and holes. The AVS model has a limited number of parameters, most of which have a physical meaning and can easily be extracted from device characterization. The model has been extensively calibrated with experimental dc I-V and s-parameter measurements of devices with gate lengths from 650 to 40 nm. This has allowed the scaling of mobility and VS source injection velocity of carriers with gate length to be investigated for the first time. The new compact model yields continuous currents and charges and can easily be used in the design and analysis of circuits and systems implemented with GFETs.

An Ambipolar Virtual-Source-Based Charge-Current Compact Model for Nanoscale Graphene Transistors

We measure top-gated graphene field-effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases by ~10% over timescales of ~10 μs, consistent with charge trapping mechanisms. The pulsed operation leads to hysteresis-free I-V characteristics that are studied with pulses as short as 75 and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple dc characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/μm. In addition, using modeling and capacitance-voltage measurements, we extract trap densities up to 1012 cm-2 in the top-gate dielectric (here Al2O3). This study illustrates important timeand field-dependent imperfections of top-gated GFETs with high-κ dielectrics, which must be carefully considered for future developments of this technology.

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Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

We present a circuit-compatible compact model of the intrinsic capacitances of graphene field-effect transistors (GFETs). Together with a compact drain current model, a large-signal model of GFETs is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits, dealing with the DC, transient behavior, and frequency response of the circuit. The drain current model is based in a drift-diffusion mechanism for the carrier transport coupled with an appropriate field-effect approach. The intrinsic capacitance model consists of a 16-capacitance matrix including self-capacitances and transcapacitances of a four-terminal GFET. To guarantee charge conservation, a Ward-Dutton linear charge partition scheme has been used. The large-signal model has been implemented in Verilog-A, being compatible with conventional circuit simulators and serving as a starting point toward the complete GFET device model that could incorporate additional non-idealities.

Large-Signal Model of Graphene Field-Effect Transistors -- Part I: Compact Modeling of GFET Intrinsic Capacitances

Graphene emerged in 2004 as the first 2-D material with exotic properties. Since then the literature has been flooded with reports, with physicists, material scientists, and engineers grabbing their respective shares. Numerous reviews have also been published. While these reviews have done excellent works in their own ways, new reports are coming up faster than they could draw the attentions of researchers. The authors, therefore, feel that there is a demanding scope for a fresh review. Further, many aspects of graphene are not covered in the reviews so far. New concept devices are also entering into the arena of graphene day by day. The purpose of this paper is therefore to present a comprehensive review on the conventional as well as novel device applications of graphene. While we believe that graphene is the material which will transform the electron devices from the classical regime to the quantum world, it is difficult to believe that it will be a complete substitute to silicon in the near future.

Graphene for Electron Devices: The Panorama of a Decade

An analytical model of the small-signal current and capacitance characteristics of radio frequency graphene field-effect transistors (GFETs) is presented. The model is based on explicit distributions of chemical potential in graphene channels (including ambipolar conductivity at high source-drain bias) obtained in the framework of drift-diffusion current continuity equation solution. Small-signal transconductance and output conductance characteristics are modeled by considering the two modes of drain current saturation, including drift velocity saturation or electrostatic pinchoff. Analytical closed expression for the complex current gain and the cutoff frequency of high-frequency GFETs are obtained. This model allows to describe an impact of parasitic resistances, capacitances, interface traps on extrinsic current gain, and cutoff frequency.

Small-Signal Capacitance and Current Parameter Modeling in Large-Scale High-Frequency Graphene Field-Effect Transistors

We study impact of the near-interfacial oxide traps on the C-V and I-V characteristics of graphene gated structures. Methods of extraction of interface trap level density in graphene field effect devices from the capacitance-voltage measurements are described and discussed. It has been found that the effects of electron-electron or hole-hole interactions and electron-hole puddles can be mixed in C-V characteristics putting obstacles in the way of uniquely determined extraction of the interface trap density in graphene. Influence of the interface traps on DC and AC capacitance and conductance characteristics of graphene field-effect structures is described. It has been shown that variety of widths of resistivity peaks in various samples could be explained by different interface trap capacitance values.

Interface Traps in Graphene Field-Effect Devices Extraction Methods and Influence on Characteristics

An analytic compact model of large-area double-gate graphene field-effect transistor is presented. As parts of the model, the electrostatics of double-gate structure is described and a unified phenomenological approach for modeling of the two drain current saturation modes is proposed.

Physics-based compact modeling of double-gate graphene field-effect transistor operation

We study theoretically an influence of the near-interfacial insulator traps and electron-hole puddles on the small-signal capacitance and conductance characteristics of the gated graphene structures. Based on the self-consistent electrostatic consideration and taking into account the interface trap capacitance the explicit analytic expressions for charge carrier density and the quantum capacitance as functions of the gate voltage were obtained. This allows to extract the interface trap capacitance and density of interface states from the gate capacitance measurements. It has shown that self-consistent account of the interface trap capacitance enables to reconcile discrepancies in universal quantum capacitance vs the Fermi energy extracted for different samples. The electron-hole puddles and the interface traps impact on transfer I-V characteristics and conductivity has been investigated. It has been shown that variety of widths of resistivity peaks in various samples could be explained by different interface trap capacitance values.

A. A. Tselykovskiy

Papers

Small-Signal Capacitance and Current Parameter Modeling in Large-Scale High-Frequency Graphene Field-Effect Transistors

Interface Traps in Graphene Field-Effect Devices Extraction Methods and Influence on Characteristics

Physics-based compact modeling of double-gate graphene field-effect transistor operation

Influence of Interface Traps and Electron-Hole Puddles on Quantum Capacitance and Conductivity in Graphene Field-Effect Transistors

Quantum Capacitance vs Chemical Potential Universal Curve and Interface Trap Parameter Extraction in Graphene Gated Structures