Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.

Integrated circuit device and fabrication using metal-doped chalcogenide materials

An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.

PCRAM memory cell and method of making same

A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.

Complementary bit PCRAM sense amplifier and method of operation

Two PCRAM cells which use a common anode between them are disclosed. The two memory cells can be accessed separately to store two bits of data which can be read and written, and can be stacked one over the other with a common anode between them to form an upper and lower cell pair. Respective access transistors are provided for the cells and arranged to permit reading and writing of the cells.

Apparatus and method for dual cell common electrode PCRAM memory device

A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

Programmable conductor random access memory and method for sensing same

Experimental results on the constant current stressing in hydrogenated amorphous silicon (a-Si:H) Cr–p+–V thin film devices are presented. With increasing injection of charge via either increasing bias or time, the current-voltage characteristics of devices exhibit instability, as shown by a decrease in the reverse current. This is interpreted in terms of the creation of defects in the a-Si:H. The defect generation rate. as measured by the voltage shift ΔV at a constant reverse current in the J-V curve, is found to follow a square-root time dependent law. In addition, a decrease in device conductance after stressing is also observed, which is described by a mechanism of dopant equilibrium during and after stressing.

A. E. Owen

Papers

Current-induced instability in Cr–p+ a-Si:H–V thin film devices