The current-voltage characteristics of a classical field-effect transistor (FET) is dictated by thermal injection of charge carriers over a gate-controlled energy barrier. It is well known that the subthreshold swing \((S)\) associated with these transistors cannot be reduced below the Boltzmann limit of 60 mV/decade, which in turn defines the lower limit of power dissipation. Therefore, a number of groups have recently proposed to use negative capacitance (NC) gate insulators in FETs to reduce \(S\) below the Boltzmann limit. The ferroelectric-FET (FE-FET) and suspended-gate FET (SG-FET) are two examples. It is now well accepted that NC-FETs can lower \(S\) , but given a specific device architecture, the question of whether there is a lower limit of \(S\) (and if so, the conditions that define the limit) has not been answered. In this paper, we: 1) demonstrate that the fundamental constraints of stability and hysteresis-free operation dictate that there is a lower limit of \(S\) associated with each NC-FET technology; 2) provide a general algorithm to calculate the minimum subthreshold swing \((S_{\rm min})\) ; and 3) illustrate the concept using SG-FET and FE-FET for two different channel configurations, namely, a bulk FET and an FET with constant channel capacitance. Our results broaden the understanding of field-effect action in NC-FETs and should inform research on these devices.

Stability Constraints Define the Minimum Subthreshold Swing of a Negative Capacitance Field-Effect Transistor

An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and the stable travel range as a function of the structural parameters. Gate position is explicitly expressed as a function of the gate voltage, thus enabling the convenient integration of the analytical SGFET relationships into the standard MOSFET models. Starting from the new SGFET model, the influence of the mechanical hysteresis on the circuit steady-state behavior is discussed, the potential of using the SGFET as an ultra-low power switch is demonstrated, and the operation of the complementary SGFET inverter is analyzed.

Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

A new electro-mechanical non-volatile memory (NVM) cell design is proposed and demonstrated for the first time. The fabricated cells operate with relatively low program/erase voltages and large sensing margin. Because only dielectric and metal layers are required, this cell design is suitable for post-CMOS fabrication. As the cell area is reduced, low operating voltages can be maintained by scaling the vertical dimensions of the cell. Nanometer-scale electro-mechanical memory technology is therefore attractive for high-density embedded memory applications.

Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration

Advances in electronics have revolutionized the way people work, play and communicate with each other. Historically, these advances were mainly driven by CMOS transistor scaling following Moore’s law, where new generations of devices are smaller, faster, and cheaper, leading to more powerful circuits and systems. However, conventional scaling is now facing major technical challenges and fundamental limits. New materials, devices, and architectures are being aggressively pursued to meet present and future computing needs, where tight integration of memory and logic, and parallel processing are highly desired. To this end, one class of emerging devices, termed memristors or memristive devices, have attracted broad interest as a promising candidate for future memory and computing applications. Besides tremendous appeal in data storage applications, memristors offer the potential to enable efficient hardware realization of neuromorphic and analog computing architectures that differ radically from conventional von Neumann computing architectures. In this review, we analyze representative memristor devices and their applications including mixed signal analog-digital neuromorphic computing architectures, and highlight the potential and challenges of applying such devices and architectures in different computing applications.

Memristive computing devices and applications

As design rule is scaled down in complementary metal-oxide-semiconductor (CMOS) device, the several disadvantages based on electric field effect in CMOS device were emerged such as short channel effect, junction leakage and gate oxide leakage current (J.D. Meindl, 2001). Non-CMOS based device using micro/nanoelectromechanical systems (MEMS/NEMS) switch have been proposed as one of the alternatives (R.L. Badzey et al., 2004), (Abele et al., 2006), (W.W. Jang et al., 2007). Devices based on MEMS/NEMS switch show excellent on-off current characteristics due to an almost zero off current and abrupt on-off current transition. Also, they have robustness under harsh environments such as X-ray, radiation, and low/high temperature. In this work, two types of two terminal NEMS switch with the smallest dimensions ever made were proposed and fabricated. Moreover, their electrical characteristics were provided.

NEMS switch with 30 nm thick beam and 20 nm high air gap for high density non-volatile memory applications

The design, operation, characterization and scalability of a 1T SG-MOSFET memory cell that combines a MOSFET solid-state device and a Micro-Electro-Mechanical gate electrode, is reported The proposed SG-MOSFET memory uses the charging of the gate dielectric by direct contact of the conductive gate with the gate insulator during mechanical pull-in, which results in I-V hysteresis Very low gate leakage and excellent current ratio in programmed logic states are demonstrated Cycling without significant degradation up to 105 cycles is experimentally shown and the scalability of the cell is explored by simulation

A. Gangadharaiah

Papers

1T MEMS Memory Based on Suspended Gate MOSFET