Adrian M. Ionescu

TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.

TL;DR: In this article, the length scaling of the double gate tunnel field effect transistor (DG tunnel FET) is studied. And the authors demonstrate that while some improvements are observed, the length scale does not dramatically affect switch figures of merit such as subthreshold slope, Ion and I off, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET.

TL;DR: In this paper, the first complete experimental demonstration and investigation of subthreshold swing, SS, smaller than 60 mV/decade, at room temperature, due to internal voltage amplification in FETs with a Metal-Ferroelectric-Metal-Oxide gate stack was reported.

TL;DR: Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05/10 as discussed by the authors.