In this paper we present a new algorithm for accelerating the potential calculation which occurs in the inner loop of iterative algorithms for solving electromagnetic boundary integral equations. Such integral equations arise, for example, in the extraction of coupling capacitances in three-dimensional (3-D) geometries. We present extensive experimental comparisons with the capacitance extraction code FASTCAP and demonstrate that, for a wide variety of geometries commonly encountered in integrated circuit packaging, on-chip interconnect and micro-electro-mechanical systems, the new "precorrected-FFT" algorithm is superior to the fast multipole algorithm used in FASTCAP in terms of execution time and memory use. At engineering accuracies, in terms of a speed-memory product, the new algorithm can be superior to the fast multipole based schemes by more than an order of magnitude.

/pdf/a-precorrected-fft-method-for-electrostatic-analysis-of-4jonxbli4x.pdf

A precorrected-FFT method for electrostatic analysis of complicated 3-D structures

The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scali ng of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance—estimating both clock rate and IPC —of an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.

/pdf/clock-rate-versus-ipc-the-end-of-the-road-for-conventional-54d15znbzi.pdf

Clock rate versus IPC: the end of the road for conventional microarchitectures

Research in automatic analysis of sign language has largely focused on recognizing the lexical (or citation) form of sign gestures as they appear in continuous signing, and developing algorithms that scale well to large vocabularies. However, successful recognition of lexical signs is not sufficient for a full understanding of sign language communication. Nonmanual signals and grammatical processes which result in systematic variations in sign appearance are integral aspects of this communication but have received comparatively little attention in the literature. In this survey, we examine data acquisition, feature extraction and classification methods employed for the analysis of sign language gestures. These are discussed with respect to issues such as modeling transitions between signs in continuous signing, modeling inflectional processes, signer independence, and adaptation. We further examine works that attempt to analyze nonmanual signals and discuss issues related to integrating these with (hand) sign gestures. We also discuss the overall progress toward a true test of sign recognition systems?dealing with natural signing by native signers. We suggest some future directions for this research and also point to contributions it can make to other fields of research. Web-based supplemental materials (appendicies) which contain several illustrative examples and videos of signing can be found at www.computer.org/publications/dlib.

/pdf/automatic-sign-language-analysis-a-survey-and-the-future-3yh2fbjd5b.pdf

Automatic Sign Language Analysis: A Survey and the Future beyond Lexical Meaning

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

The contribution of plant root systems to slope stability and soil erosion control has received a lot of attention in recent years. The plant root system is an intricate and adaptive object, and understanding the details of soil–root interaction is a difficult task. Although the morphology of a root system greatly influences its soil-fixing efficiency, limited architectural work has been done in the context of slope stabilization and erosion control, and hence it remains unknown exactly which characteristics are important. Many of the published research methods are tedious and time-consuming. This review deals with the underlying mechanisms of shallow slope stabilization and erosion control by roots, especially as determined by their architectural characteristics. The effect of soil properties as well as the relative importance of different root sizes and of woody versus non-woody species are briefly discussed. Empirically and intuitively, architectural features seem to determine the effect of root systems on erosion phenomena and an effort is therefore made here to link both aspects. Still, the research to underpin this relationship is poorly developed. A variety of methods are available for detailed root system architectural measurement and analysis. Although, generally time-consuming, a full 3D architectural description followed by analysis in software such as AMAPmod offers the possibility to extract relevant information on almost any root system architectural characteristic. Combining several methods of measurement and analysis in a complementary way may be a useful option, especially in a context of modelling.

The role of fine and coarse roots in shallow slope stability and soil erosion control with a focus on root system architecture: a review

An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. This paper proposes a Boundary Element Method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification.In contrast with standard BE methods, we propose a Green's function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor.

/pdf/extraction-of-circuit-models-for-substrate-cross-talk-4xvutc8mx6.pdf

Extraction of circuit models for substrate cross-talk

In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract circuits containing many thousands of substrate terminals. Examples are given that show that the method is sufficiently accurate for practical circuit verification. The method has been implemented in the layout-to-circuit extractor Space.

/pdf/fast-computation-of-substrate-resistances-in-large-circuits-2g6hfwp6nx.pdf

Fast computation of substrate resistances in large circuits

We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the conductor charges are approximated by a piece-wise linear function on a web of edges located on the surface of the conductors. This yields a system of Green's function integral equations that is solved by a novel approximate matrix inversion technique that only utilizes the entries corresponding to pairs of finite elements that are physically close to each other. With N representing the size of the layout, this results in time and space complexities of O(N) and O(PIN) respectively. The method has been implemented in an efficient layout to circuit extractor and experimental results are presented.

An Efficient Finite Element Method for Submicron IC Capacitance Extraction

Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package

The authors describe a method to find RC models for (nonorthogonal) interconnections in VLSI layouts, including resistances as well as ground and coupling capacitances. The method starts with the construction of a finite-element mesh for the interconnection polygons. Resistances are assigned to the edges of the mesh, and capacitances to the vertices. Then, all internal nodes are eliminated by a novel and efficient node-reduction algorithm. This algorithm preserves the Elmore time constants between the remaining nodes, without actually computing them. The resulting network accurately reflects the electrical properties of the distributed RC interconnections, and can efficiently be simulated. >

http://ieeexplore.ieee.org/iel2/706/573/00015415.pdf

A.J. van Genderen

Papers

Extraction of circuit models for substrate cross-talk

Fast computation of substrate resistances in large circuits

An Efficient Finite Element Method for Submicron IC Capacitance Extraction

Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package

Extracting simple but accurate RC models for VLSI interconnect