Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

Field Programmable Gate Array Applications—A Scientometric Review

Internet of Things (IoT) is connecting billions of devices to the Internet. These IoT devices chain sensing, computation, and communication techniques, which facilitates remote data collection and analysis. wireless sensor networks (WSN) connect sensing devices together on a local network, thereby eliminating wires, which generate a large number of samples, creating a big data challenge. This IoT paradigm has gained traction in recent years, yielding extensive research from an increasing variety of perspectives, including scientific reviews. These reviews cover surveys related to IoT vision, enabling technologies, applications, key features, co-word and cluster analysis, and future directions. Nevertheless, we lack an IoT scientometrics review that uses scientific databases to perform a quantitative analysis. This paper develops a scientometric review about IoT over a data set of 19,035 documents published over a period of 15 years (2002–2016) in two main scientific databases (Clarivate Web of Science and Scopus). A Python script called ScientoPy was developed to perform quantitative analysis of this data set. This provides insight into research trends by investigating a lead author’s country affiliation, most published authors, top research applications, communication protocols, software processing, hardware, operating systems, and trending topics. Furthermore, we evaluate the top trending IoT topics and the popular hardware and software platforms that are used to research these trends.

https://www.mdpi.com/2073-8994/9/12/301/pdf

Internet of Things: A Scientometric Review

In this paper, we give attention to the robustness of the Cyber-Physical System, which consists of interdependent physical resources and computational resources. Numerous infrastructure systems can evolve into the Cyber-Physical System, e.g., smart power grids, traffic control systems, and wireless sensor and actuator networks. These networks depend on their interdependent networks, which provide information or energy to function. In a Cyber-Physical System, a small failure could trigger serious cascading failures within the entire interdependent networks. In this paper, we try to alleviate these cascading failures between interdependent networks to reduce losses. We discuss the robustness of systems for random attacks by calculating the size of functioning components in entire networks. We change the inter-links topology of the coupled networks to enhance the reliability of the entire system. Then we get the most effective swapping strategy in enhancing the robustness of the Cyber-Physical System compared to previous studies. Different systems’ structures would influence the performance of swap inter links strategies on improving the reliability of networks. Moreover, our work could guide how to optimize a Cyber-Physical System topology by reducing the influence of cascading failures.

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Security Analysis of CPS Systems Under Different Swapping Strategies in IoT Environments

Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems

The smart mobile Internet-of-things (IoT) network lays the foundation of the fourth industrial revolution, the era of hyperconnectivity, hyperintelligence, and hyperconvergence. As this revolution gains momentum, the security of smart mobile IoT networks becomes an essential research topic. This study aimed to provide comprehensive insights on IoT security. To this end, we conducted a systematic mapping study of the literature to identify evolving trends in IoT security and determine research subjects. We reviewed the literature from January 2009 to August 2020 to identify influential researchers and trends of keywords. We additionally performed structural topic modeling to identify current research topics and the most promising ones via topic trend estimation. We synthesized and interpreted the results of the systematic mapping study to devise future research directions. The results obtained from this study are useful to understand current trends in IoT security and provide insights into research and development of IoT security.

/pdf/current-research-trends-in-iot-security-a-systematic-mapping-14gdd6vzuv.pdf

Current Research Trends in IoT Security: A Systematic Mapping Study

Lightweight cryptographic solutions are required to guarantee the security of Internet of Things (IoT) pervasiveness. Cryptographic primitives mandate a non-linear operation. The design of a lightweight, secure, non-linear 4 × 4 substitution box (S-box) suited to Internet of Things (IoT) applications is proposed in this work. The structure of the 4 × 4 S-box is devised in the finite fields GF (24) and GF ((22)2). The finite field S-box is realized by multiplicative inversion followed by an affine transformation. The multiplicative inverse architecture employs Euclidean algorithm for inversion in the composite field GF ((22)2). The affine transformation is carried out in the field GF (24). The isomorphic mapping between the fields GF (24) and GF ((22)2) is based on the primitive element in the higher order field GF (24). The recommended finite field S-box architecture is combinational and enables sub-pipelining. The linear and differential cryptanalysis validates that the proposed S-box is within the maximal security bound. It is observed that there is 86.5% lesser gate count for the realization of sub field operations in the composite field GF ((22)2) compared to the GF (24) field. In the PRESENT lightweight cipher structure with the basic loop architecture, the proposed S-box demonstrates 5% reduction in the gate equivalent area over the look-up-table-based S-box with TSMC 180 nm technology.

https://www.mdpi.com/2078-2489/9/1/13/pdf

Lightweight S-Box Architecture for Secure Internet of Things

Objective: This paper presents the Field Programmable Gate Array (FPGA) implementations of the different block cipher mode architectures of the ISO standardized light weight block cipher PRESENT, designed for resource constrained devices. Methods/ Statistical Analysis: The performance evaluations compare the implementations of the different block cipher modes, namely Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback Mode (CFB), Output Feed Back Mode (OFB) and CounTeR (CTR) mode for the PRESENT cipher. The throughput of encryption of three successive 64 bit blocks of data ranges from 565.312Mbps to 574.784Mbps for the modes other than the cipher feedback mode in the Spartan-3 FPGA. The throughput for providing confidentiality through encryption in the cipher feedback mode arrives as 68.912 Mbps, 155.392Mbps and 300.8 Mbps for a 64 bit block of data for the input streams of size 8 bits, 16 bits and 32 bits respectively. Findings: The throughput of the block cipher mode hardware architectures of the light weight cipher PRESENT demonstrates the high speed performance of the cipher in encryption/decryption of data as blocks and streams. Application/ Improvement: The significance of the proposed work is to know the hardware performance of the different modes of operation for the light weight block cipher PRESENT. The performance estimation of the block cipher modes operations of the PRESENT cipher definition in hardware have been carried out for the first time.

FPGA Implementation and Analysis of the Block Cipher Mode Architectures for the PRESENT Light Weight Encryption Algorithm

Background: With the advent in hand held mobile computing devices, the demand for high performance compact processors is increasing. In this work a processor is designed with hardwired instructions for elementary mathematical functions like sine, cosine, sinh, cosh, division and multiplication. Methods: The processor employs Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of the above mentioned instructions. The parallel and pipelined implementation of the processor is carried out. The pipelined processor is configured as waveform generator. The novelty of this work is the integration of both trigonometric and hyperbolic operations in the same processor. Findings: ASIC Implementation is carried out with 40nm technology libraries. The parallel processor so designed operates at maximum frequency of 24.23 MHz and pipelined processor operates at maximum frequency of 261.36 MHz. Conclusion: This increase in operating frequency is achieved at the cost of increased silicon area and optimal power dissipation. The waveform generator generates sine, cosine waves of 3.5 MHz and sine hyperbolic, cosine hyperbolic waves and exponential waves of 7.9 MHz. The limitation being the waveform generator generates waves of constant frequency. Additional circuit is required in generating waves of different frequencies.

Design and Implementation of a Generic CORDIC Processor and its Application as a Waveform Generator

Cryptography is the art of realizing security by the strength of mathematics involved in the security algorithm, the security is compromised by the mathematics of cryptanalysis using the side channel attacks. Differential power analysis (DPA) is the most effective form of side channel power analysis, which analyses the power consumption of the cryptographic device statistically and reveals the secret information. This paper investigates the implementation of the S-BOX with the DPA resistant logical style, namely, the Three Phase Dual rail Pre-charge logic (TDPL) which makes the power consumption of the device insensitive to intermediate values. To make the power consumption constant an additional phase is added in addition to the pre-charge and evaluation phases of the three phase dual rail logic. In this paper, the implementation of the S-BOX is carried out in both the static CMOS logic and the TDPL logic to compare their DPA resistance. It is proved that the static CMOS logic is more vulnerable to power analysis than the considered three phase logic. The correlation analysis is performed to estimate the property of the DPA resistance of the S-box implementation.

A. Prathiba

Papers

Lightweight S-Box Architecture for Secure Internet of Things

Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems

FPGA Implementation and Analysis of the Block Cipher Mode Architectures for the PRESENT Light Weight Encryption Algorithm

Design and Implementation of a Generic CORDIC Processor and its Application as a Waveform Generator

DPA resistance analysis of the cryptographic S-box implementation in static CMOS and TDPL logic style