Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal.

Logic circuit and method of logic circuit design

In this paper CMOS compatible Gate Diffusion Input (GDI) design technique is proposed. The GDI method enables the implementation of a wide range of complex logic functions using only two transistors. This method is suitable for the design of low-power logic gates, with a much smaller area than Static CMOS and existing PTL techniques. As opposite to our originally proposed GDI logic, the modified GDI logic is fully compatible for implementation in a standard CMOS process. Simulations of basic GDI gates under process and temperature corners in 40nm CMOS process are shown and compared to similar CMOS gates. We show that while having the same delay, GDI gates achieve leakage and active power reduction of up to 70% and 50%, respectively.

Gate Diffusion Input (GDI) logic in standard CMOS nanoscale process

This paper proposes four low power adder cells using different XOR and XNOR gate architectures. Two sets of circuit designs are presented. One implements full adders with 3 transistors (3-T) XOR and XNOR gates. The other applies Gate-Diffusion-Input (GDI) technique to full adders. Simulations are performed by using Hspice based on 180nm CMOS technology. In comparison with Static Energy Recovery Full (SERF) adder cell module, the proposed four full adder cells demonstrate their advantages, including lower power consumption, smaller area, and higher speed.

Novel low power full adder cells in 180nm CMOS technology

A full adder is one of the most commonly used digit circuit components, many improvements have been made to refine the architecture of a full adder. In this paper, 4 different types of 10 transistor (10-T) based full adder are proposed using a new design methodology called GDI (gate-diffusion input). In the meantime, a complete verification and comparison is also carried out to test the performance of the proposed adders. According to our test results, one of the proposed 10-T full adders is better than the prior designs which makes it a better alternative.

Novel 10-T full adders realized by GDI structure

GDI (gate diffusion input)-a new technique of low power digital combinatorial circuit design-is described. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. A detailed design methodology is described. Performance comparison with traditional CMOS and PTL design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay and power dissipation. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported.

A. Wagner

Papers

Gate-diffusion input (GDI)-a novel power efficient method for digital circuits: a design methodology