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Adi Fuchs
Researcher at Princeton University
Publications - 9
Citations - 301
Adi Fuchs is an academic researcher from Princeton University. The author has contributed to research in topics: Cache & Open architecture. The author has an hindex of 6, co-authored 9 publications receiving 218 citations. Previous affiliations of Adi Fuchs include Mellanox Technologies & Technion – Israel Institute of Technology.
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Proceedings ArticleDOI
OpenPiton: An Open Source Manycore Research Framework
Jonathan Balkind,Michael McKeown,Yaosheng Fu,Tri Nguyen,Yanqi Zhou,Alexey Lavrov,Mohammad Shahrad,Adi Fuchs,Samuel Payne,Xiaohua Liang,Matthew Matl,David Wentzlaff +11 more
TL;DR: OpenPiton is the world's first open source, general-purpose, multithreaded manycore processor and framework that leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design.
Proceedings ArticleDOI
Disruptive prefetching: impact on side-channel attacks and cache designs
Adi Fuchs,Ruby B. Lee +1 more
TL;DR: This work suggests the use of specialized prefetching algorithms for the purpose of protecting from cache-based side-channel attacks, and integrated their policies with commonly used GHB and stride prefetcher schemes, and compared their performance with the standard implementations of those schemes.
Proceedings ArticleDOI
The Accelerator Wall: Limits of Chip Specialization
Adi Fuchs,David Wentzlaff +1 more
TL;DR: This work characterizes how current accelerators depend on CMOS scaling, based on a physical modeling tool that is constructed using datasheets of thousands of chips, and builds a model which projects forward to see what future gains can and cannot be enabled from chip specialization.
Proceedings ArticleDOI
Loop-Aware Memory Prefetching Using Code Block Working Sets
TL;DR: This paper presents the code block working set (CBWS) prefetcher, which captures the working set of complete loop iterations using a single context and improves the performance of existing prefetchers when dealing with tight loops.
Proceedings ArticleDOI
Scaling datacenter accelerators with compute-reuse architectures
Adi Fuchs,David Wentzlaff +1 more
TL;DR: The COmpute-REuse Accelerators (COREx) architecture that shifts computations from the scalability-hindered transistor-based logic towards the continuing-to-scale storage domain, and achieves an average speedup of 6.4x and average savings of 50% in energy and 63% inEnergy-delay product.