Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is $189.73\mu W$ which is 63% of the state-of-the-art.

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RECON: Resource-Efficient CORDIC-Based Neuron Architecture

The principle of redundant binary representation is used to design power and area efficient signed Vedic $8\times 8$ multiplier architecture. The Urdhva Tiryakbhyam Sutra, which extends Vedic algorithms to signed numbers has been implemented in this work. The design is written in VHDL and synthesized on FPGA device using Xilinx ISE 14.4. In contrast to the traditional architectures considered, the proposed architecture performs better in terms of power.

A Low Power Signed Redundant Binary Vedic Multiplier

Neural networks provide high performance in solving different types of issues, and their complexity increases accordingly to the complexity of the application and requires high computational power. The solution to the productivity problem is associated with the creation of specialized hardware for the implementation of neural networks in the form of application-specific integrated circuits. The main elements of a neural network are data storage blocks, adders and multipliers. This paper demonstrates variants of multiplier acceleration using methods of multiplication by a group of bits. We propose variants of layout implementations of the considered high-speed multipliers allowing to reach a compromise between their performance and the area of the chip.

Analysis of Multiplier Architectures for Neural Networks Hardware Implementation

Multiplier and Adder are the primary components to design a MAC unit. It has two stage of operations; one is to find the product of two numbers and other is adding the product to the other number and stores it in the accumulator. Power, Delay and LUT utilization are the important parameters to decide the performance of a processors. Introducing Reversible logic gates which dissipate less power compared to Conventional logic. Vedic Multiplier is one of the efficient multipliers to decrease the delay and improve the performance. Also, various reversible adders are constructed to add the partial outputs. The proposed work shows the performance of different designs used in a MAC unit using reversible logic.

Design and Comparison of Power, Area and Delay of 32-bit Reversible MAC unit

BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator

Multiply and Accumulate (MAC) is one of the primary operations used widely in signal-processing and other applications. Multiplier is the fundamental component of Digital Signal Processors (DSP’s).Its parameters such as power, LUT utilization and delay decides the performance of a DSP. So, there is a need to design a power and delay efficient multiplier. In this paper, a 16-bit MAC unit is designed using an 8-bit vedic multiplier and carry-save adder. A comparison with the existing 8-bit vedic multiplier using Square-Root (SQR) Carry-Select Adder (CSLA) is presented. It is compared with a conventional array-multiplier. The entire design is implemented in Verilog HDL. Synthesis and simulations were done using Xilinx ISE Design Suite 14.5 and Vivado 2018.2. The proposed design achieves significant improvement in area and delay. In addition, a reduction in power around 9.5% is achieved.

Akella Srinivasa Krishna Vamsi

Papers

An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics