Proceedings ArticleDOI
An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics
Akella Srinivasa Krishna Vamsi,S R Ramesh +1 more
- pp 0319-0322
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TLDR
A 16-bit MAC unit is designed using an 8-bit vedic multiplier and carry-save adder that achieves significant improvement in area and delay and is compared with a conventional array-multiplier.Abstract:
Multiply and Accumulate (MAC) is one of the primary operations used widely in signal-processing and other applications. Multiplier is the fundamental component of Digital Signal Processors (DSP’s).Its parameters such as power, LUT utilization and delay decides the performance of a DSP. So, there is a need to design a power and delay efficient multiplier. In this paper, a 16-bit MAC unit is designed using an 8-bit vedic multiplier and carry-save adder. A comparison with the existing 8-bit vedic multiplier using Square-Root (SQR) Carry-Select Adder (CSLA) is presented. It is compared with a conventional array-multiplier. The entire design is implemented in Verilog HDL. Synthesis and simulations were done using Xilinx ISE Design Suite 14.5 and Vivado 2018.2. The proposed design achieves significant improvement in area and delay. In addition, a reduction in power around 9.5% is achieved.read more
Citations
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A Low Power Signed Redundant Binary Vedic Multiplier
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Analysis of Multiplier Architectures for Neural Networks Hardware Implementation
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TL;DR: Vedic Multiplier is one of the efficient multipliers to decrease the delay and improve the performance and introduces Reversible logic gates which dissipate less power compared to Conventional logic.
References
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Journal ArticleDOI
Low Power High Speed 16x16 bit Multiplier using Vedic Mathematics
TL;DR: A simple digital multiplier architecture based on the Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra of Vedic Mathematics is presented and an improved technique for low power and high speed multiplier of two binary numbers (16 bit each) is developed.
Proceedings ArticleDOI
Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder
R Balakumaran,E Prabhu +1 more
TL;DR: A novel method for multiplier and accumulator is proposed by combining reversible logic functions and hybrid carry look-ahead adder, which shows better performance compare to conventional method and has advantages of reduced area overhead and critical path delay.
Proceedings ArticleDOI
Design and optimization of 16×16 Bit multiplier using Vedic mathematics
TL;DR: In this article, the concept of Urdhwa-Tiryagbhyam is used i.e., vertically and crosswise multiplication to implement 16×16 bit Vedic multiplier and optimization is achieved by using carry save adders.
Proceedings ArticleDOI
Design of MAC unit in artificial neural network architecture using Verilog HDL
TL;DR: A new processing unit, Vedic multiplier with square root carry select adder (SQRT-CSLA) is designed, overcomes the drawbacks of the existing system, and it's also providing better performance of the entire network.
Journal Article
Parallel multiplier-accumulator unit based on Vedic mathematics
TL;DR: The critical path delay of the proposed design is significantly reduced and it outperforms the existing designs and is elevated by the efficient use of higher order compressors in the merged partial product compression and accumulator (PPCA) architecture.
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