Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.

Plasma processes for depositing low dielectric constant films

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

Methods of depositing a silicon oxide layer on a substrate are described. The methods may include the steps of providing a substrate to a deposition chamber, generating an atomic oxygen precursor outside the deposition chamber, and introducing the atomic oxygen precursor into the chamber. The methods may also include introducing a silicon precursor to the deposition chamber, where the silicon precursor and the atomic oxygen precursor are first mixed in the chamber. The silicon precursor and the atomic oxygen precursor react to form the silicon oxide layer on the substrate, and the deposited silicon oxide layer may be annealed. Systems to deposit a silicon oxide layer on a substrate are also described.

Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen

A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects

Integrated low k dielectrics and etch stops

The semiconductor device consists of a substrate (201) and an intermediate layer insulating film (204) or a passivation insulating film each formed on the substrate. They each contain silicon, oxygen, carbon and hydrogen the carbon content being no less than the silicon content. The insulation film can have a dielectric constant of 1.8 to 3.2 and the atomic ratio of carbon to silicon in the insulation film can be 1 to 3. A surface layer of the insulation film can have a higher viscosity than the remainder of the film.

Semiconductor device for LSI devices

We present an insulator with a dielectric constant lower than 3.0, thermal stability up to 500° C and good gap-filling characteristics. This insulator was formed by downstream plasma chemical vapor deposition (CVD) at room temperature using tetra-methylsilane (TMS)/O2 gases. It contained a large amount of water in the as-deposited state. Annealing at 350° C resulted in a decrease in the water content of the insulator, and the insulator did not absorb water after the annealing. The film is constructed from Si–O and Si–CH3 bonds, which produce a low dielectric constant and high thermal stability.

Low dielectric constant insulator formed by downstream plasma CVD at room temperature using TMS/O2

Reliable techniques for extracting the gate dielectric layer thickness from capacitance-voltage (C-V) characteristics are essential for manufacturing process quality control. Continued reduction of the dielectric layer thickness has brought about a need for new measurement procedures which can account for the direct tunneling currents through the gate insulator. We present a guideline for performing two-frequency C-V analysis of sub-2 nm gate oxides and show that it is possible to extract the dielectric layer thickness with an error of less than 4%. We show that in order to achieve this level of accuracy, it is necessary to choose the measurement frequencies and the test device size so that the dissipation remains below 1.1 at least at one of the two measurement frequencies.

Applicability limits of the two-frequency capacitance measurement technique for the thickness extraction of ultrathin gate oxide

PROBLEM TO BE SOLVED: To form an insulating film which is less affected by troubles such as film stress and film reduction induced in a condensation CVD method by a method wherein a series of processes composed of a modification process which modifies a condensed film and a condensed film forming process is repeatedly carried out. SOLUTION: A semiconductor substrate 113 is kept at a low temperature, a vapor intermediate is condensed on a semiconductor substrate 113 through the reaction of a film forming gas composed of oxygen radical gas and organic silane gas, whereby a silicon oxide condensed film is formed on the semiconductor substrate 113. Then, nitrogen gas is made flow through the hollow structure of a substrate support 114 as oxygen radical keeps flowing, a tungsten flash lamp 127 and an ultraviolet lamp 128 are turned on (modification process), and the condensed film is thermally treated in an atmosphere of oxygen radical. One cycle of processes composed of a condensed film forming process and a modification process is repeatedly carried out a few times, whereby a silicon film which has a very small impurity content and film reduction and prescribed thickness (thick enough to fill up a groove completely) is formed.

Manufacture of semiconductor device and semiconductor manufacturing equipment

A nonvolatile semiconductor memory device comprising: a gate electrode portion comprising: a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type, separated from the substrate by a tunnel insulating film; an inter-electrode insulating film formed on the floating gate electrode and formed of a stacked structure film of at least one type of high dielectric permittivity material; and a control gate electrode formed above the inter-electrode insulating film; and at least one interface layer between the inter-electrode insulating film and the floating gate electrode or the inter-electrode insulating film and the control gate electrode; source and drain regions of a second conductivity type which are formed on the main surface of the substrate with the gate electrode portion being arranged between the source and drain regions.

Akiko Nara

Papers

Semiconductor device for LSI devices

Low dielectric constant insulator formed by downstream plasma CVD at room temperature using TMS/O2

Applicability limits of the two-frequency capacitance measurement technique for the thickness extraction of ultrathin gate oxide

Manufacture of semiconductor device and semiconductor manufacturing equipment

Nonvolatile semiconductor memory and manufacturing method for the same