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Albert G. Greenberg
Researcher at Bell Labs
Publications - 49
Citations - 1891
Albert G. Greenberg is an academic researcher from Bell Labs. The author has contributed to research in topics: Parallel algorithm & Communication channel. The author has an hindex of 21, co-authored 49 publications receiving 1846 citations. Previous affiliations of Albert G. Greenberg include Mathematical Sciences Research Institute & AT&T.
Papers
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Journal ArticleDOI
Stability of binary exponential backoff
TL;DR: Simulation results are reported that indicate alternative retransmission protocols can significantly improve performance, and it is established that binary exponential backoff is stable if the sum of the arrival rates is sufficiently small.
Journal ArticleDOI
How fair is fair queuing
Albert G. Greenberg,Neal Madras +1 more
TL;DR: Two variants of the fair queuing discipline are considered, and rigorously establish their fairness wa sample path comparisons with the head-of-line processor sharing disclphne, a mathematical idealization that prowdes a fairness paradigm.
Patent
Apparatus and method for dynamic resource allocation in wireless communication networks utilizing ordered borrowing
Mathilde South Orange Benveniste,Albert G. Greenberg,Frank Kwangming Warren Hwang,Boris D. Lubachevsky,Paul E. Wright +4 more
TL;DR: In this article, the authors propose a method of ordered borrowing which facilitates dynamic access to a global channel set that has been partitioned into subsets, with each cell of the system being assigned a particular subset of the channel set.
Journal ArticleDOI
A lower bound on the time needed in the worst case to resolve conflicts deterministically in multiple access channels
TL;DR: In this paper, a general model of deterministic algorithms to resolve conflicts is introduced, and it is established that time must elapse in the worst case before all transmission attempts to resolve a conflict succeed.
Proceedings ArticleDOI
Hardware-efficient fair queueing architectures for high-speed networks
TL;DR: A collection of self-clocked fair queueing (SCFQ) architectures amenable to efficient hardware implementation in network switches are presented, demonstrating that these architectures divide link bandwidth fairly on a small time scale, preserving connection bandwidth and burstiness properties.