Showing papers by "Alberto Prieto published in 1991"

CMOS current-mode multivalued PLAs

Abstract: A programmable logic array (PLA) structure for implementation of multivalued combinational and sequential systems is proposed. The PLA is integrable by using a conventional CMOS process and makes a NOR/TSUM two-level implementation of multivalued functions, which can consume less silicon area than an equivalent binary implementation. Pseudo-nMOS and dynamic CMOS implementations for the proposed PLA are also presented, using current-mode inputs and outputs. Since these PLAs operate with several current levels, a significant saving in silicon area can be obtained in comparison with binary PLAs. A four-valued PLA prototype was manufactured using an ordinary CMOS process. Experimental data for this prototype show that the chip operates correctly without significant deterioration in the current levels.

Application of Vector Quantization Algorithms to Protein Classification and Secondary Structure Computation

Abstract: In this paper a feature-map based system for protein classification according to circular dichroism spectra is described. The training algorithm has been developed from Kohonen LVQ (Learning Vector Quantization) optimized to get maximum efficiency. As a result, proteins with different secondary structure are clearly separated through a completely unsupervised training process. The algorithm is able to extract features from a high-dimensional vector (CD spectra) and map it to a 2-dimensional network. A new tool has been developed to test LVQ performance, which can be used to fine tune some of LVQ algorithm parameters. Secondary structure for unknown proteins can also be computed, giving better results than classical methods. A 3D solid representation has been introduced to represent 3D feature maps.

The fast Tamari transform

Abstract: The fast Tamari transform (FTT), which is suitable to obtain some properties of p-valued digital functions and networks (p being the power of a prime) is presented. A systematic procedure to calculate the FTT is defined, and an expression for the complexity of calculation, and flow-graphs and networks for the calculation of the FTT are also presented. All aspects are illustrated with several examples.

An Approach to Isolated Word Recognition Using Multilayer Perceptrons

Abstract: Neural networks offer the potential of providing massive parallelism, adaptation, and new algorithm approaches to speech recognition. In this communication, we show a new approach to face the problem of speaker-independent isolated word recognition with the Multilayer Perceptron (MLP), trained with Backpropagation algorithm. This approach lies in a preprocessing similar to that used for Kohonen Networks, thus in the context of unsupervised learning, which allows to overcome the temporal alignment problem of word samples and to reduce the number of neurons in the MLPs. As a preliminary result, the performances of MLPs for recognizing sequences of vowels in isolated words, after learning with samples of isolated vowels, are presented.

Using Reed-Muller coefficients to synthesise optimal prediction modules for concurrent testing

Abstract: This Letter shows that the synthesis of the extra circuitry required for testing a digital circuit during its normal operation is a problem of selecting an optimal set of Reed-Muller spectral coefficients. To obtain acceptable solutions for this NP-complete problem, an algorithm based on simulated annealing is proposed.

Optimization Problems on Concurrent Testing Solved by Neural Networks

Abstract: This communication presents an Extended Hopfield Neural Network which has been applied to design the extra circuitry for testing a digital circuit during its normal operation, problem which we have shown to be equivalent to the problem of selecting an optimal set of Reed-Muller spectral coefficients. It has been suggested that neural networks, in particular the Hopfield Neural network, may be used to solve linear programming problems. Here, we show how a modification of the Hopfield Network structure also allows to solve non-linear programming problems.

Universal built-in self-test procedure for CMOS PLA's

Abstract: The authors present a built-in self-test (BIST) programmable logic array (PLA) design in CMOS technology that provides a high percentage of coverage for multiple stuck-at, crosspoint, and bridging faults and, furthermore detects all simple stuck-open faults in the AND and OR planes and all multiple stuck-open faults in the AND plane. As the test patterns used are the same for all PLAs, a universal test for PLAs is defined. The hardware overhead complexity for this scheme resembles that of previous proposals, although the number of different test patterns used has been reduced. >

CMOS Implementation of Synapse Matrices with Programmable Analog Weights

Abstract: Synapse matrices can be considered as basic building blocks for hardware emulators of Artificial Neural Networks. A great number of today's models use weighted sums in partial or fully connected artificial neurons; these computations being efficiently carried out by analog CMOS current-mode circuits. In this communication several alternative analog CMOS multipliers, as basic cells for synapse matrices with dynamically programmable weights, are summarised; and an enhanced implementation of such cells is presented. A chip including a 8×16 multiplier synapse matrix has been manufactured using a conventional 2µm CMOS process. The synaptic weights are dynamically modifiable and temporary memorized as analog voltages in the capacitive gates of MOS transistors. While maintaining simplicity, the basic cell in the matrix preserves the stored weight against input/outputs changes. The designed prototype has a density of 50 synapses per square millimetre, including the circuitry for individual weight actualization of each synapse in the matrix. Some experimental results demonstrating the functionality of the circuit are also reported.

Implementation and applications of multivalued decoders

Abstract: A synthesis procedure is described for multivalued threshold decoders and their application to the implementation of multivalued functions. This method is based on the definition of inversion and extreme functions. Decoders are obtained using only the very simple blocks which synthesize inversion functions. This general design procedure may be used for any integrated circuit technology. As an example, the method is applied to the synthesis of an integrated CMOS quaternary decoder. Both the layout and the timing of the integrated circuit, and their application to the synthesis of multivalued functions and multistable memory elements, are shown.

CMOS Implementation of a Cellular Neural Network with Dynamically Alterable Cloning Templates

Abstract: An analog CMOS implementation of a Cellular Neural Network with modifiable cloning templates is proposed. One of the most important difficulties to hardware implement neural networks is their topological complexity which implies a high number of interconnections among cells. Nevertheless, as in cellular neural network each cell is only connected to its neighbour cells, their hardware implementation is easier. Even though the reduced connectivity of cellular neural networks, they are suitable for different tasks in the domain of image processing. For each particular application, the cloning templates that characterise the cellular network have to be changed. The circuit here presented allows the online modification of cloning templates, and is integrable using a conventional CMOS process. Some simulation results of the designed circuits are also presented.

Characterization and design of hybrid-mode CMOS circuits

Abstract: This aper rovides an analysis of the static and dynamic working of the basic building blocks for hybrid-mode CMOS circuits. As a result of the analysis, simplified expressions are obtained which are adequate for the electrical design. layout and erformances evaluation of these integrated circuits. The aper also includes SPICE simulation results roving the validity of the models developed