Showing papers by "Alessandro Trifiletti published in 2008"

High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips

Abstract: The design flow of a digital cryptographic device must take into account the evaluation of its security against attacks based on side channels observation. The adoption of high level countermeasures, as well as the verification of the feasibility of new attacks, presently require the execution of time-consuming physical measurements on the prototype product or the simulation at a low abstraction level. Starting from these assumptions, we developed an exploration approach centered on high level simulation, in order to evaluate the actual implementation of a cryptographic algorithm, being it software or hardware based. The simulation is performed within a unified tool based on SystemC, that can model a software implementation running on a microprocessor-based architecture or a dedicated hardware implementation as well as mixed software-hardware implementations with cycle-accurate resolution. Here we describe the tool and provide a large set of design explorations and characterizations based on actual implementations of the AES cryptographic algorithm, demonstrating how the execution of a large set of experiments allowed by the fast simulation engine can lead to important improvements in the knowledge and the identification of the weaknesses in cryptographic algorithm implementations.

Enhancing power analysis attacks against cryptographic devices

Abstract: A current-measuring technique is introduced, which promises to substantially enhance power analysis attacks against cryptographic co-processors. The proposed technique exploits an active circuit to measure the instantaneous current consumption of a device under attack while supplying, at the same time, the device with a stable voltage. Higher gain-bandwidth product, higher sensitivity and lower insertion error are the main advantages with respect to a resistor-based measurement. Experimental results when the proposed circuit is used to measure the current consumption of an FPGA are reported, and the achievable advantage in terms of sensitivity is discussed. Results of a differential power analysis attack are reported too.

A new dynamic differential logic style as a countermeasure to power analysis attacks

Abstract: Power analysis attacks exploit the existence of ldquoside channelsrdquo in implementations of cryptographic algorithms to extract secret data. The scientific literature reports consolidated methods - such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) - for extracting a secret cryptographic key through the sensing of the hardware power consumption. We propose a novel dynamic and differential CMOS logic style as a countermeasure against power attacks on cryptographic devices. The proposed logic family exploits the idea of using signals with 3 possible states and operates with power consumption ideally independent on both the logic values and the sequence of data. We have designed a set of logic gates, flip flops and a simple S-BOX, and compared the S-BOX against previously published secure logic styles in terms of transistor count, power consumption and correlation between data and power dissipation.

Switched Capacitor Sample-and-Hold Circuit with Input Signal Range beyond Supply Voltage

Abstract: A switched capacitor sample-and-hold (S/H) circuit with extended dynamic range beyond the supply voltage is presented. The proposed architecture includes a gate-bootstrapped circuit and an improved flip-around S/H with two selectable configurations. Simulations in a 0.13 ?m CMOS technology show that the new system is capable of sampling a below-ground signal and allows an interface adapter that enhances the dynamic range of the low-voltage analog-to-digital (A/D) converters without affecting the input bandwidth.

Unity-Gain Amplifier With Theoretically Zero Gain Error

Abstract: This paper presents a unity-gain amplifier architecture, which, unlike already known solutions, provides a theoretically zero gain error without requiring an infinitely large loop gain. The architecture is based on two amplifiers nested in a feedback configuration, which allows a straightforward complementary metal-oxide-semiconductor (CMOS) implementation. Performances are analytically evaluated and compared to those of the traditional solution under similar design settings. Simulations using a 0.35-mum CMOS process are found to be in agreement with theory, and Monte Carlo simulations have also shown the robustness of the proposed approach against process tolerances.

Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems

Abstract: Temperature measurement is becoming increasingly important in integrated circuits and microsystems; nevertheless, existing techniques for the integration of high accuracy, high precision temperature sensors are not optimal for deep sub-micron CMOS processes. Here we describe a low voltage, low power, compact, high accuracy, high precision temperature sensor for deep sub-micron CMOS systems; our approach takes advantage of charge balancing and charge sharing for low current consumption, does not use resistors for compactness, and takes advantage of both PTAT and autozero techniques for high accuracy and high precision; the circuit can be operated at low supply voltages. As a proof of concept, we report transistor level simulations in a standard 0.13 mum process; the sensor only sinks about 6 muA from a 1.2 V supply voltage, achieving a power dissipation as low as 7.2 muW.

A low-power sample-and-hold circuit based on a switched-opamp technique

Abstract: A novel low-power and high-performance sample-and-hold (S/H) front-end suitable for pipelined and cyclic analog-to-digital converters using 0.25-mum CMOS technology is proposed. This sampler uses a new S/H architecture exploiting a switched telescopic cascode operational transconductance amplifier (OTA) to minimize power consumption. Simulation results show that the proposed solution allows simple and reliable S/H function and an effective power reduction without noise and distortion penalty.

Mixed-signal flexible architecture for the synthesis of n-port networks

Abstract: We present a flexible mixed-signal architecture for the synthesis of an n-port analog network. It exploits a field programmable gate array as digital processing element and second generation current conveyors as analog input/output blocks. To validate the approach, a prototype is realized for the basic case of a two-port network and experimental results in agreement with those expected are provided.

A simple technique for fast digital background calibration of A/D converters

Abstract: A modification of the background digital calibration procedure for A/D converters by Li and Moon is proposed, based on a method to improve the speed of convergence and the accuracy of the calibration. The procedure exploits a colored random sequence in the calibration algorithm, and can be applied both for narrowband input signals and for baseband signals, with a slight penalty on the analog bandwidth of the converter. By improving the signal-to-calibration-noise ratio of the statistical estimation of the error parameters, our proposed technique can be employed either to improve linearity or to make the calibration procedure faster. A practical method to generate the random sequence with minimum overhead with respect to a simple PRBS is also presented. Simulations have been performed on a 14-bit pipeline A/D converter in which the first 4 stages have been calibrated, showing a 15 dB improvement in THD and SFDR for the same calibration time with respect to the original technique.

Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems

Abstract: In CMOS smart sensors and microsystems it can be very convenient to integrate both analog and digital circuits in the same chip; since the supply voltage for high-accuracy, high- precision interfaces should be as immune from disturbances as possible, low drop out regulators are often necessary. Here we show a CMOS, dual op amp, fast, low drop out regulator which allows to diminish the power supply gain by orders of magnitude up to very high frequencies.