Showing papers by "Alessandro Trifiletti published in 2014"

Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations

Abstract: This paper extends the analysis of the effectiveness of Leakage Power Analysis (LPA) attacks to cryptographic VLSI circuits on which circuit level countermeasures against Differential Power Analysis (DPA) are adopted. Security metrics used for assessing the DPA-resistance of crypto core implementations, such as the minimum number to disclosure (MTD) and the asymptotic correlation coefficient, have been extended to the case of LPA. The LPA-resistance has been evaluated in terms of MTD as a function of the on chip noise. Noise variances up to 10000 times greater than the signal variance have been taken into account and LPA attacks have been successfully executed for all the logic styles under analysis using less than 100000 measurements. Moreover the role of process variations has been investigated through extensive Monte Carlo simulations in order to evaluate their impact on the leakage model for the logic styles under analysis. Results show that LPA attacks can be successfully carried out on the different anti-DPA logic styles even in presence of process variations. To the best of our knowledge, this work proves for the first time the effectiveness of LPA attacks in a real scenario where on chip noise and process variations are taken into account.

88- A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors

Abstract: The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensitivity and measure accuracy irrespectively of the input parasitic capacitance. Therefore, the main limitation of all previous current-mode techniques is nearly eliminated. Besides, as an additional distinctive aspect, the proposed solution is suitable for both linear- and hyperbolic-type capacitive sensors. To validate the idea an interface circuit was designed in a 65-nm CMOS technology powered from a 2.5-V supply and dissipating 88- μA standby current. Measurements show that relative capacitive sensor variations up to ± 900 fF ( ± 100% of the nominal value) even in presence of a large parasitic capacitance of 2.5 pF are detected in less than 1 μs with a sensitivity of about 5 nA/fF and with an relative error lower than ± 1.5%, without requiring digital calibration.

A Novel Wake-Up Receiver with Addressing Capability for Wireless Sensor Nodes

Abstract: Emerging low-power radio triggering techniques for wireless motes are a promising approach to prolong the lifetime of Wireless Sensor Networks (WSNs). By allowing nodes to activate their main transceiver only when data need to be transmitted or received, wake-up-enabled solutions virtually eliminate the need for idle listening, thus drastically reducing the energy toll of communication. In this paper we describe the design of a novel wake-up receiver architecture based on an innovative pass-band filter bank with high selectivity capability. The proposed concept, demonstrated by a prototype implementation, combines both frequency-domain and time-domain addressing space to allow selective addressing of nodes. To take advantage of the functionalities of the proposed receiver, as well as of energy-harvesting capabilities modern sensor nodes are equipped with, we present a novel wake-up-enabled harvesting-aware communication stack that supports both interest dissemination and converge casting primitives. This stack builds on the ability of the proposed WuR to support dynamic address assignment, which is exploited to optimize system performance. Comparison against traditional WSN protocols shows that the proposed concept allows to optimize performance tradeoffs with respect to existing low-power communication stacks.

Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher

Abstract: In this work the effectiveness of Leakage Power Analysis (LPA), a new class of side-channel attacks against cryptographic circuits, has been demonstrated on a case study. LPA attacks have been mounted against a bit slice implementation of the Serpent block cipher. After having measured the leakage contribution of a bit slice unit inside the processor, chosen as selection function for LPA attacks, an adequate power model has been identified. In order to consider the on-chip noise due to the static consumption of the other logics inside the processor, an estimation of the SNR has been provided according to the count of equivalent gates. The bit slice sub-block has been designed in a 65nm CMOS technology node for different logic styles, i.e. CMOS, WDDL, MDPL, and SABL. Simulations show that for each logic implementation the correct key of the algorithm has been recovered with a maximum of 50.000 measurements, demonstrating that LPA attack can be successfully carried out against a wide range of logic styles, even if they efficiently thwart standard DPA and CPA attacks. Static power is expected to become greater in downscaled technologies, and thus LPA must be considered a serious threat for the security of cryptographic VLSI circuits.

Experiments on two clock countermeasures against power analysis attacks

Abstract: Two countermeasures against DPA/CPA attacks have been designed, tested and compared on an AES encoding coprocessor implemented on FPGA. Both countermeasures are based on altering the clock signal and can be readily implemented at RTL design stage. Experimental results based on first order CPA attacks confirmed the effectiveness of both the countermeasures in protecting the SBOX output, showing that even with the acquisition of 300000 power curves, the encryption key can't be revealed by the relevant correlation peaks.

Implementing radar algorithms on CUDA hardware

Abstract: This paper investigates the implementation of radar algorithms on Graphics Processing Units (GPUs). The focus is on electronically scanned search radars. GPUs enable to develop high performance digital processing systems with limited development time. It is possible to employ a single commercial board (an NVIDIA GeForce 680 GTX in our case) to perform all the algorithms of a search radar: downconversion, amplitude/phase correction, pulse compression, beam forming, spectrum analysis, and CFAR noise floor estimation.

Architecture and modeling of a novel optical beamforming network suitable for microwave photonics implementation

Abstract: A novel architecture for optical beamforming is presented, and its implementation as an integrated multi-chip system is discussed. Modeling and design methodology of the key components of the system, i.e. the linearized electro-optic external modulator and the array of tunable true delay lines, is detailed. Measurements on a linearized modulator are presented to demonstrate the feasibility of the proposed design approach.

Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer

Abstract: A novel topology of lossy equalizer with impedance transformation and stabilization capability is presented, which allows the design of broadband very high-linearity and high-power amplifiers. Design equations are presented and used to design a 1-2.4 GHz 60W composite amplifier exploiting push-pull configuration.

Using feed array networks to control distortions in antenna reflector for astrophysical radio-astronomy

Abstract: In this paper we present a methodology to calibrate and correct frequency-dependent errors in phased-array antennas with large signal bandwidth and large size. If the receivers are not narrow-band, the hypotheses of constant gain and group delay are not valid. If the frequency responses of the receivers are affected by mismatches, this will also impact directivity. Standard Amplitude and Phase Correction (APC) algorithms will not be effective in this case, and a more advanced complex FIR filtering algorithm is used. A transmitted signal is assumed to be known in order to provide a reference and estimate the optimal calibration coefficients of the FIR filters.

Microwave fiber optic link linearization by design-oriented analytic model

Abstract: An analytic design-oriented model of microwave optical link has been developed. The core of the model is the non-linear and noise model of a Mach-Zehnder LiNbO3 interferometer. Different linearized microwave links, based on the use of an auxiliary modulator, have been designed by using the proposed model: significant improvement of the 3rd-order intermodulation attenuation has been measured on a lab test bed.

Cosmic non-TEM radiation and synthetic feed array sensor system in ASIC mixed signal technology

Abstract: The paper deals with the opportunity to introduce “Not strictly TEM waves” Synthetic detection Method (NTSM), consisting in a Three Axis Digital Beam Processing (3ADBP), to enhance the performances of radio telescope and sensor systems. Current Radio Telescopes generally use the classic 3D “TEM waves” approximation Detection Method, which consists in a linear tomography process (Single or Dual axis beam forming processing) neglecting the small z component. The Synthetic FEED ARRAY three axis Sensor SYSTEM is an innovative technique using a synthetic detection of the generic “NOT strictly TEM Waves radiation coming from the Cosmo, which processes longitudinal component of Angular Momentum too. Than the simultaneous extraction from radiation of both the linear and quadratic information component, may reduce the complexity to reconstruct the Early Universe in the different requested scales. This next order approximation detection of the observed cosmologic processes, may improve the efficacy of the statistical numerical model used to elaborate the same information acquired. The present work focuses on detection of such waves at carrier frequencies in the bands ranging from LF to MMW. The work shows in further detail the new generation of on line programmable and reconfigurable Mixed Signal ASIC technology that made possible the innovative Synthetic Sensor. Furthermore the paper shows the ability of such technique to increase the Radio Telescope Array Antenna performances.

Feed array metrology and correction layer for large antenna systems in ASIC mixed signal technology

Abstract: The paper deals with a possible use of the feed array present in a large antenna system, as a layer for measuring the antenna performance with a self-test procedure and a possible way to correct residual errors of the Antenna geometry and of the antenna distortions. Focus has been concentrated on a few key critical elements of a possible feed array metrology program. In particular, a preliminary contribution to the design and development of the feed array from one side, and the subsystem dedicated to antenna distortion monitoring and control from the other, have been chosen as the first areas of investigation. Scalability and flexibility principles and synergic approach with other coexistent technologies have been assumed of paramount importance to ensure ease of integrated operation and therefore allowing in principle increased performance and efficiency. The concept is based on the use of an existing feed array grid to measure antenna distortion with respect to the nominal configuration. Measured data are then processed to develop a multilayer strategy to control the mechanical movable devices (when existing) and to adjust the residual fine errors through a software controlled phase adjustment of the existing phase shifter The signal from the feed array is converted passing through a FPGA/ASIC level to digital data channels. The kind of those typically used for the scientific experiments. One additional channel is used for monitoring the antenna distortion status. These data are processed to define the best correction strategy, based on a software managed control system capable of operating at three different levels of the antenna system: reflector rotation layer, sub reflector rotation and translation layer (assuming the possibility of controlling a Stewart machine), phase shifter of the phased array layer. The project is at present in the design phase, a few elements necessary for a sound software design of the control subsystem have been developed at a technological demonstrator level while the ASIC board for generating the digital data stream has been fully developed. A prototype for control accurately the position of the sub-reflector up to a diameter of 5 meters (similar to the sub reflector size of a large antenna) using a Stewart mechanism is being planned. The selection strategy of the correction modes will depend on the dynamics of the phased array (i.e. the available bits of the A/D conversion). The reaction time allowed for the correction, depending on the error type and the inertia of the sub systems. Typically, the compensation can be divided among all the adjusting elements.