다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

In wireless environments, transmission and reception costs dominate system power consumption, motivating research effort on new technologies capable of reducing the footprint of the radio, paving the way for the Internet of Things. The most important challenge is to reduce power consumption when receivers are idle, the so called idle-listening cost. One approach proposes switching off the main receiver, then introduces new wake-up circuitry capable of detecting an incoming transmission, optionally discriminating the packet destination using addressing, then switching on the main radio only when required. This wake-up receiver technology represents the ultimate frontier in low power radio communication. In this paper, we present a comprehensive literature review of the research progress in wake-up radio (WuR) hardware and relevant networking software. First, we present an overview of the WuR system architecture, including challenges to hardware design and a comparison of solutions presented throughout the last decade. Next, we present various medium access control and routing protocols as well as diverse ways to exploit WuRs, both as an extension of pre-existing systems and as a new concept to manage low-power networking.

/pdf/ultra-low-power-wake-up-radios-a-hardware-and-networking-55kvi6zf2s.pdf

Ultra Low Power Wake-Up Radios: A Hardware and Networking Survey

https://www.dtc.umn.edu/s/resources/bib05eurasip.pdf

Bibliography on cyclostationarity

In this paper, we propose a simple, yet reliable methodology to expedite yield estimation and optimization of microwave structures. In our approach, the analysis of the entire response of the structure at hand (e.g., $S$ -parameters as a function of frequency) is replaced by response surface modeling of suitably selected feature points. On the one hand, this is sufficient to determine whether a design satisfies given performance specifications. On the other, by exploiting the almost linear dependence of the feature points on the designable parameters of the structure, reliable yield estimates can be realized at low computational cost. Our methodology is verified using two examples of waveguide filters and one microstrip hairpin filter and compared with conventional Monte Carlo analysis based on repetitive electromagnetic simulations, as well as with statistical analysis exploiting linear response expansions around the nominal design. Finally, we perform yield-driven design optimizations on these filters.

Rapid Yield Estimation and Optimization of Microwave Structures Exploiting Feature-Based Statistical Analysis

The present invention relates to an antenna device for a portable radio communication device adapted for receiving and/or transmitting radio signals in at least a first and a second operating frequency band, said antenna device comprising a half-loop radiating element, comprising a feeding portion and a grounding portion, and arranged to operate at FM frequencies. The antenna device comprises a capacitor at said feeding portion and an inductor at said grounding portion, and said half-loop radiating element is arranged to simultaneously with FM frequencies operate at frequencies at least ten times higher than FM frequencies, wherein said capacitor is arranged to short circuit said half-loop radiating element to ground for frequencies at least ten times higher than FM frequencies and said inductor is arranged to short circuit said half-loop radiating element to ground for FM frequencies.

Antenna device and portable radio communication device comprising such antenna device

Emerging low-power radio triggering techniques for wireless motes are a promising approach to prolong the lifetime of Wireless Sensor Networks (WSNs). By allowing nodes to activate their main transceiver only when data need to be transmitted or received, wake-up-enabled solutions virtually eliminate the need for idle listening, thus drastically reducing the energy toll of communication. In this paper we describe the design of a novel wake-up receiver architecture based on an innovative pass-band filter bank with high selectivity capability. The proposed concept, demonstrated by a prototype implementation, combines both frequency-domain and time-domain addressing space to allow selective addressing of nodes. To take advantage of the functionalities of the proposed receiver, as well as of energy-harvesting capabilities modern sensor nodes are equipped with, we present a novel wake-up-enabled harvesting-aware communication stack that supports both interest dissemination and converge casting primitives. This stack builds on the ability of the proposed WuR to support dynamic address assignment, which is exploited to optimize system performance. Comparison against traditional WSN protocols shows that the proposed concept allows to optimize performance tradeoffs with respect to existing low-power communication stacks.

http://senseslab.di.uniroma1.it/administrator/components/com_jresearch/files/publications/A_Novel_wake_up_Receiver_with_.pdf

A Novel Wake-Up Receiver with Addressing Capability for Wireless Sensor Nodes

The use of short-length III-V technologies is required to design circuits for microwave and millimetre-wave applications showing state-of-the-art performance. The parameter dispersion of such processes requires design techniques to achieve the best trade-off between performance and yield. External control of MMIC bias, based on process parameters estimation, allows yield enhancement even when design centring or feedback-based controls are not effective. A methodology to perform yield-oriented design of MMICs in III-V technologies is proposed. A set of on-chip circuits is used to estimate the value of process parameters; an external controller corrects the bias point in order to achieve the design centring in a parameter region around the estimated values. The proposed technique corrects circuit performance in the presence of parameter values belonging to the distribution tail, where standard techniques fail. The design centring approach and a distance-dependent correlated statistical model of HEMTs are used to design the external controller. The proposed methodology has been applied to design both a transimpedance amplifier and a distributed amplifier for multi-gigabit applications, showing a yield improvement of more than 10% with respect to the design centring approach, and encouraging the use of the proposed methodology for circuit design with short-length III-V technologies.

MMIC yield optimisation by design centring and off-chip controllers

An improvement of a standard fully differential class-AB symmetrical operational transconductance amplifier (OTA) topology is proposed in this brief to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional to the input common-mode component is generated through a simple low-current auxiliary amplifier and used to modulate a bias voltage, achieving cancellation of the output common-mode component. Simulations in 40-nm CMOS technology show a net improvement of common-mode rejection ratio without affecting differential-mode behavior; the increase in area and power consumption is minimal, with a tradeoff between power and settling time. Simulations of a sample-and-hold exploiting the proposed OTA are presented.

A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR

A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB behaviour and full rail-to-rail operation when closed in unity-gain buffer configuration.

A 0.6 V class-AB rail-to-rail CMOS OTA exploiting threshold lowering

The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative type VCII (VCII−). Interestingly, the same analysis shows that no canonic oscillator configuration can be achieved using positive type VCII (VCII+), since a single VCII+ does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator configurations are the only possible ones and make use of two resistors, two capacitors and a single VCII−. Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range.

Pasquale Tommasino

Papers

A Novel Wake-Up Receiver with Addressing Capability for Wireless Sensor Nodes

MMIC yield optimisation by design centring and off-chip controllers

A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR

A 0.6 V class-AB rail-to-rail CMOS OTA exploiting threshold lowering

A New VCII Application: Sinusoidal Oscillators