An ESD simulation flow that has been demonstrated on 14 nm products is described. Due to Moore's Law, ESD protection devices are having an increasingly large impact on silicon area, power, and capacitance. A number of real-world examples demonstrating how the simulation flow improved these areas are provided.

A full-chip ESD simulation flow

6. Analog-to-Digital ESD Design Synthesis

Analog ESD and Latchup Design Rule Checking and Verification

We present a successfully implemented dynamic ESD simulation, verification and analysis tool, DynEsdChecker, that can simulate the ESD event on the layout containing RC extractions, can generate full chip ESD verification results, can provide user with guidelines on how to revise the design to meet the ESD design target.

https://ieeexplore.ieee.org/iel5/6034620/6045562/06045602.pdf

A predictive full chip dynamic ESD simulation and analysis tool for analog and mixed-signal ICs

This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.

Auxiliary self-protecting transistor structure

A system includes undervoltage protection circuitry coupled in parallel with electronic circuitry configured to receive a supply voltage from a power supply. The undervoltage protection circuitry is configured to shunt undervoltage current resulting from an undervoltage transient in the supply voltage away from the electronic circuitry.

Alister Young

Papers

A predictive full chip dynamic ESD simulation and analysis tool for analog and mixed-signal ICs

Auxiliary self-protecting transistor structure

Undervoltage protection system

Auxiliary self-protecting transistor circuit, system and method