One of the most common means for diagnosis is through medical laboratory testing, which primarily uses venous blood as a sample. This requires an invasive method by cannulation that needs proper vein selection. The use of a vein finder would help the phlebotomist to easily locate the vein, preventing possible pre-analytical error in the specimen collection and even more discomfort and pain to the patient. This paper is a review of the scientific publications on the different developed low-cost vein finder prototypes utilizing camera assisted near infrared (NIR) light technology. Methods: Electronic databases were searched online, these included PubMed (PMC), MEDLINE, Science Direct, ResearchGate, and Institute of Electrical and Electronics Engineers (IEEE) Xplore digital library. Specifically, publications with the terms vein finder prototype, NIR technology, vein detection, and infrared imaging were screened. In addition, reference lists were used to further review related publications. Results: Cannulation challenges medical practitioners because of the different factors that can be reduced by the utilization of a vein finder. A limited number of publications regarding the assessment of personnel performing cannulation were observed. Moreover, variations in methodology, number of patients, type of patients according to their demographics and materials used in the assessment of the developed prototypes were noted. Some studies were limited with regard to the actual human testing of the prototype. Conclusions: The development of a low-cost effective near infrared (NIR) vein finder remains in the phase of improvement. Since, it is being challenged by different human factors, increasing the number of parameters and participants/human for actual testing of the prototypes must also be taken into consideration for possible commercialization. Finally, it was noted that publications regarding the assessment of the performance of phlebotomists using vein finders were limited.

https://www.mdpi.com/1424-8220/19/16/3573/pdf

Vein Pattern Locating Technology for Cannulation: A Review of the Low-Cost Vein Finder Prototypes Utilizing near Infrared (NIR) Light to Improve Peripheral Subcutaneous Vein Selection for Phlebotomy.

Space-borne synthetic aperture radar (SAR) and optical sensors are important tools for building damage detection. Fusion of SAR and optical images improves detection performance. However, when the resolutions of the two different kinds of images differ, the performance of the existing pixel-level fusion methods deteriorates significantly due to interpolation-induced distortion. To solve this problem, this paper presents a new superpixel-based belief fusion (SBBF) model for building damage detection. The superpixels on the SAR and optical images are identified by the segmentation on the pre-earthquake optical image to perform the fusion on the superpixel-level instead of the pixel-level in existing methods. Then in the fusion stage, different from the commonly used direct fusion methods that do not consider the reliability in the fusion process, a novel belief fusion method that employs a basic belief assignment (BBA) to incorporate different reliabilities of superpixels is proposed to improve the accuracy of building damage detection. For each superpixel, the BBA is assigned based on the influence of noise and resolutions. The United Nations Operational Satellite Applications Programme (UNOSAT) datasets corresponding to the 2010 Haiti earthquake and the 2011 Tōhoku earthquake, are used to evaluate the performance of the proposed method. The experimental results show that the proposed method achieves significantly better performance than existing separate SAR or optical images based methods, and the existing pixel-level fusion methods.

Building Damage Detection via Superpixel-Based Belief Fusion of Space-Borne SAR and Optical Images

A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/−0.5 LSB and +0.8/−0.9 LSB, respectively. The ADC consumes 435- $\mu \text{W}$ of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 $\mu \text{m}$ show that it is suitable for column-parallel readout in CMOS image sensors.

A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC

The explosive growth of digital imaging, especially in the fields of medicine, education, and e-commerce, has made data maintenance and transmission over networks a daunting task. Therefore, the development and use of image compression techniques have become vital for overcoming the problems of storage and transmission of digital image data. Two methods that are extensively used for data compression are Discrete Cosine Transformation and Discrete Wavelet Transform (DWT). In our present study, we have shown the benefits of a DWT-based approach by utilizing the canonical Huffman coding as an entropy encoder. DWT decomposes the image into different sub-bands. These sub bands are known as approximate image and detail images. The approximate image is normalized in the range (0, 1) for obtaining the Canonical Huffman coding bit stream. In a similar way, details coefficients are also normalized in the range (0, 1) for obtaining the canonical Huffman coding bit stream of detail images. Hard thresholding is often used to discard insignificant coefficients of detail images. Our proposed method takes less computing time and has a smaller codebook size than that of conventional Huffman coding. Moreover, the results show an improvement over Wavelet Scalar Quantization often used for image compression of fingerprints. We have applied our method to various popular images and obtained promising PSNR, CR, and BPP that highlight the advantages of our approach and the efficiency of our algorithms.

Canonical Huffman Coding Based Image Compression using Wavelet

A superpixel based on-chip compression is proposed in this paper. Pixels are compared in spatial domain and the pixels with similar characteristics are grouped to form the superpixels. Only one pixel corresponding to each superpixel is read to achieve the compression. The on-chip compression circuit is designed and simulated in UMC 180 nm CMOS technology. For 70% compression, the proposed design results in about 33% power saving. The reconstruction of the compressed image is performed off-chip using bilinear interpolation. Further, two enhancement approaches are developed to improve the output image quality. The first approach is based on wavelet decomposition whereas the second approach uses a deep convolutional neural network. The proposed reconstruction technique takes two orders of magnitude lesser time as compared to the state-of-the-art technique. On an average, it results in peak signal to noise ratio (PSNR) and structural similarity index measure values of 30.999 and 0.9088 dB, respectively, for 70% compression in natural images. On the other hand, the best values observed from the existing approaches for the two metrics are 28.634 and 0.8115 dB, respectively. Further, the proposed technique is found useful for thermal image compression and reconstruction. The experiment shows that the compression of 86.2% can be achieved using the threshold of two intensity levels and the compressed image can be reconstructed with the PSNR of 45.87 dB.

Content Driven On-Chip Compression and Time Efficient Reconstruction for Image Sensor Applications

A 12-bit, 1 MS/s, two-stage cyclic ADC, with novel 2.5-bit/cycle architecture is proposed in this paper. A 1.5-bit algorithm is used in a 2.5-bit framework, which reduces the required number of accurate comparators and power consumption by 42%. Further, the ADC shows 46% improvement in the conversion rate as compared to the state-of-the-art two-stage cyclic ADC. The proposed ADC is designed and fabricated in a standard 180 nm CMOS technology. The obtained values of DNL and INL are +0.5/-0.5 LSB and +0.8/-0.9 LSB respectively. The ADC consumes 0.8 mW of power and occupies an area of 0.045 mm2 with a FoM of 0.19 pJ/conversion-step. The proposed ADC when designed in a column pitch of 5.6 μm, will result in a frame-rate of 1000 frames/sec for a 1 Mpixel array.

A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors

A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated in UMC 180 nm CMOS technology. Circuit consumes total power of 4.289 μW while operating at the clock frequency of 20 MHz. Measurement results proved that the designed comparator requires maximum of three clock cycles to perform switching for the input range 250–850 mV.

A low power low latency comparator for ramp ADC in CMOS imagers

A compressive acquisition technique for on-array image compression is proposed in this paper. It capitalizes on representation ability of accumulated spatial gradients of the acquired scene. The local variations inferred from strength of the accumulated gradients are used as cues to vary number of samples read through the image sensor readout. Such sampling enables the reconstruction using traditional interpolation techniques with desired quality. The proposed method is first verified using MATLAB simulations, where on an average, a compression of 87% is achieved, for a threshold of 40 intensity levels. The images are reconstructed using nearest neighbour interpolation (NNI) method which results in a mean peak signal to noise ratio (PSNR) value of 29.09 dB. The reconstructed images are further enhanced using deep convolutional neural network, which improves the PSNR to 32.46 dB. The biggest advantage of the proposed technique is low-complex hardware design. As a proof of concept, a hardware implementation of the technique is performed using discrete components. Pixel intensity values of standard images are converted into analog voltages using a data acquisition system and mapped in the input voltage range of 1.5 V −5.5 V. For a threshold of 3.8 V, the compression of 81% - 83% is observed for the considered images. The proposed technique is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.

Amandeep Kaur

Papers

A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC

A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors

A low power low latency comparator for ramp ADC in CMOS imagers

Content Driven On-Chip Compression and Time Efficient Reconstruction for Image Sensor Applications

On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients