Journal ArticleDOI
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC
TLDR
The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption and the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate.Abstract:
A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/−0.5 LSB and +0.8/−0.9 LSB, respectively. The ADC consumes 435- $\mu \text{W}$ of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 $\mu \text{m}$ show that it is suitable for column-parallel readout in CMOS image sensors.read more
Citations
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Journal ArticleDOI
On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients
TL;DR: The proposed compressive acquisition technique for on-array image compression is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.
Proceedings ArticleDOI
A reconfigurable cyclic ADC for biomedical applications
Amandeep Kaur,Deepak Mishra +1 more
TL;DR: A reconfigurable cyclic ADC that saves readout power and reduces data acquisition rate of analog to digital converter (ADC) and also reduces the digital data content is presented.
Proceedings ArticleDOI
A 13-Bit High Speed Two-Step Single Slope ADC Design Method for Hundreds of Mpxiel CMOS Image Sensors
TL;DR: The proposed 13-bit fully parallel two-step single slope (TS-SS)ADC design method is based on the idea of time sharing and time compression, advances the fine conversion time to the coarse conversion time period, and solves the time redundancy problem of the traditional method.
Journal ArticleDOI
High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor
TL;DR: In this article , a high-speed fully differential two-step ADC design method for high frame rate CMOS image sensors was proposed, which was based on differential ramp and time-to-digital conversion (TDC) technology.
References
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Journal ArticleDOI
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Boris Murmann,Bernhard E. Boser +1 more
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
Journal ArticleDOI
A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input
TL;DR: The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption to achieve 14-b accuracy without calibration or dithering.
Journal ArticleDOI
A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs
TL;DR: The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB.
Journal ArticleDOI
A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters
Kazuya Kitamura,Toshihisa Watabe,T. Sawamoto,Tomohiko Kosugi,T. Akahori,Takashi Iida,Keigo Isobe,Takashi Watanabe,Hiroshi Shimamoto,Hiroshi Ohtake,Satoshi Aoyama,Shoji Kawahito,Norifumi Egami +12 more
TL;DR: A 33-megapixel 120-frames/s CMOS image sensor has been developed and the pipelined operation of the two cyclic ADCs reduces the conversion time and effectively lowers the power consumption.
Journal ArticleDOI
A Low-Power Pilot-DAC Based Column Parallel 8b SAR ADC With Forward Error Correction for CMOS Image Sensors
TL;DR: A compact 8b SAR ADC measuring only 348 μm×7 μm is described, which uses a new pilot-DAC (pDAC) technique to reduce the power consumption in its capacitor array and the accuracy of the pDAC scheme is protected by a novel mixed-signal Forward Error Correction (FEC) algorithm with minimal circuit overhead.