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Journal ArticleDOI

A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC

TL;DR: The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption and the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate.
Abstract: A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/−0.5 LSB and +0.8/−0.9 LSB, respectively. The ADC consumes 435- $\mu \text{W}$ of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 $\mu \text{m}$ show that it is suitable for column-parallel readout in CMOS image sensors.
Citations
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Journal ArticleDOI
TL;DR: The proposed compressive acquisition technique for on-array image compression is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.
Abstract: A compressive acquisition technique for on-array image compression is proposed in this paper. It capitalizes on representation ability of accumulated spatial gradients of the acquired scene. The local variations inferred from strength of the accumulated gradients are used as cues to vary number of samples read through the image sensor readout. Such sampling enables the reconstruction using traditional interpolation techniques with desired quality. The proposed method is first verified using MATLAB simulations, where on an average, a compression of 87% is achieved, for a threshold of 40 intensity levels. The images are reconstructed using nearest neighbour interpolation (NNI) method which results in a mean peak signal to noise ratio (PSNR) value of 29.09 dB. The reconstructed images are further enhanced using deep convolutional neural network, which improves the PSNR to 32.46 dB. The biggest advantage of the proposed technique is low-complex hardware design. As a proof of concept, a hardware implementation of the technique is performed using discrete components. Pixel intensity values of standard images are converted into analog voltages using a data acquisition system and mapped in the input voltage range of 1.5 V −5.5 V. For a threshold of 3.8 V, the compression of 81% - 83% is observed for the considered images. The proposed technique is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.

6 citations

Proceedings ArticleDOI
01 Oct 2019
TL;DR: A reconfigurable cyclic ADC that saves readout power and reduces data acquisition rate of analog to digital converter (ADC) and also reduces the digital data content is presented.
Abstract: Bio-signals such as electroencephalogram (EEG) contain low activity regions often called B-noise and high activity regions called active potentials. The high activity regions are more important as compared to their counterpart. In addition, the signals are considerably sparse in the low activity regions. Thus a full n-bit conversion of low activity samples into digital domain increases readout power and reduces data acquisition rate of analog to digital converter (ADC). To alleviate these problems, a reconfigurable cyclic ADC is presented in this paper. Input range and conversion cycles of the proposed ADC are varied according to the samples of the neural signal. The high activity region samples are resolved using conventional n-bits, however, the low activity region is resolved using less number of bits. This saves readout power and also reduces the digital data content. The proposed ADC is designed and fabricated in UMC 180 nm CMOS technology. The ADC operates at a sampling rate of 200 kS/s and consumes 61.8 µW of power. The chip occupies an area of 0.031 mm2. Using reconfiguration, the power saving of 28.6% is achieved compared to the conventional n-bit full conversion.

2 citations


Cites background from "A 12-bit, 2.5-bit/Phase Column-Para..."

  • ...A multi-bit/cycle two-stage cyclic ADC is presented in [9], where the design constraints of second stage are relaxed for power efficiency....

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Proceedings ArticleDOI
13 May 2022
TL;DR: The proposed 13-bit fully parallel two-step single slope (TS-SS)ADC design method is based on the idea of time sharing and time compression, advances the fine conversion time to the coarse conversion time period, and solves the time redundancy problem of the traditional method.
Abstract: This paper proposes a 13-bit fully parallel two-step single slope (TS-SS)ADC for high speed CMOS image sensors. The ADC design method is based on the idea of time sharing and time compression, advances the fine conversion time to the coarse conversion time period, and solves the time redundancy problem of the traditional method. Based on the 55nm1P4M CMOS process, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are simulated to be =0.8/−0.8 LSB and +2.1/−3.5LSB, respectively. The Conversion time of the 13-bit ADC is 512 ns. The effective number of bits (ENOB) is 11.33 bits and the power consumption is $47 \mu$ W.

1 citations

Journal ArticleDOI
01 Jan 2023-Sensors
TL;DR: In this article , a high-speed fully differential two-step ADC design method for high frame rate CMOS image sensors was proposed, which was based on differential ramp and time-to-digital conversion (TDC) technology.
Abstract: The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS

1 citations

References
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Journal ArticleDOI
09 Feb 2003
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
Abstract: Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-/spl mu/m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm/sup 2/.

555 citations


"A 12-bit, 2.5-bit/Phase Column-Para..." refers background in this paper

  • ...5-bit stage consists of six comparators and an MDAC [6]....

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Journal ArticleDOI
TL;DR: The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption to achieve 14-b accuracy without calibration or dithering.
Abstract: This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V.

302 citations


"A 12-bit, 2.5-bit/Phase Column-Para..." refers background in this paper

  • ...Furthermore, the multibit stage has the higher gain, which reduces the noise, matching, and settling requirements for the later stages [5]....

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  • ...where k is a proportionality constant, N1 is the number of bits resolved in the first cycle, Ctotal corresponds to the total stage capacitance, and N is the ADC resolution [5]....

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Journal ArticleDOI
TL;DR: The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB.
Abstract: A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented The simplified single-ended circuits for the cyclic ADC are squeezed into a 56-mum-pitch single-side column The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB An ultralow vertical fixed pattern noise of 01 erms - is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mus) The implemented CIS with 018-mum technology operates at 390 frames/s and has 707-V/lx middots sensitivity, 61- muV/e- conversion gain, 49-erms - read noise, and less than 04 LSB differential nonlinearity

111 citations


"A 12-bit, 2.5-bit/Phase Column-Para..." refers background or methods in this paper

  • ...Therefore, the comparators are usually designed with preamplifier as the first stage followed by the regenerative latch [4], [8]....

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  • ...The multibit stage along with the pipelined operation shows more than three-time and five-time improvement in the conversion rate than the cyclic ADCs in [4] and [8], respectively....

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  • ...Due to narrow pixel-pitch, it is difficult to isolate the sensitive analog signals from the digital feedback signals of the DAC [8]....

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Journal ArticleDOI
TL;DR: A 33-megapixel 120-frames/s CMOS image sensor has been developed and the pipelined operation of the two cyclic ADCs reduces the conversion time and effectively lowers the power consumption.
Abstract: A 33-megapixel 120-frames/s (fps) CMOS image sensor has been developed. The 7808 × 4336 pixel 2.8-μm pixel pitch CMOS image sensor with 12-bit, column-parallel, two-stage, cyclic analog-to-digital converters (ADCs) and 96 parallel low-voltage differential signaling output ports operates at a data rate of 51.2 Gb/s. The pipelined operation of the two cyclic ADCs reduces the conversion time. This ADC architecture also effectively lowers the power consumption by exploiting the amplifier function of the cyclic ADC. The CMOS image sensor implemented with 0.18-μm technology exhibits a sensitivity of 0.76 V/lx·s without a microlens and a random noise of 5.1 erms- with no column amplifier gain and 3.0erms- with a gain of 7.5 at 120 fps while dissipating only 2.45 and 2.67 W, respectively.

77 citations


"A 12-bit, 2.5-bit/Phase Column-Para..." refers background or methods in this paper

  • ...Therefore, the comparators are usually designed with preamplifier as the first stage followed by the regenerative latch [4], [8]....

    [...]

  • ...The multibit stage along with the pipelined operation shows more than three-time and five-time improvement in the conversion rate than the cyclic ADCs in [4] and [8], respectively....

    [...]

  • ...The ADCs reported in [3] and [4] internally use 1....

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  • ...In two-stage architectures, the power and settling constraints of the second stage are relaxed, which results in low power consumption [4]....

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Journal ArticleDOI
TL;DR: A compact 8b SAR ADC measuring only 348 μm×7 μm is described, which uses a new pilot-DAC (pDAC) technique to reduce the power consumption in its capacitor array and the accuracy of the pDAC scheme is protected by a novel mixed-signal Forward Error Correction (FEC) algorithm with minimal circuit overhead.
Abstract: Successive-Approximation-Register (SAR) Analog- to-Digital Converters (ADC) have been shown to be suitable for low-power applications at aggressively scaled CMOS technology nodes. This is desirable for many mobile and portable applications. Unfortunately, SAR ADCs tend to incur significant area cost and reference loading due to the large capacitor array used in its Digital-to-Analog Converter (DAC). This has traditionally made it difficult to implement large numbers of SAR ADC in parallel. This paper describes a compact 8b SAR ADC measuring only 348 μm×7 μm. It uses a new pilot-DAC (pDAC) technique to reduce the power consumption in its capacitor array; moreover, the accuracy of the pDAC scheme is protected by a novel mixed-signal Forward Error Correction (FEC) algorithm with minimal circuit overhead. Any DAC error made during pDAC operation can be recovered later by an additional switching phase. Prototype measurements in 0.18 μm technology shows that the DAC's figure-of-merit (FoM) is reduced from 61.3 fJ/step to 39.8 fJ/step by adopting pDAC switching with no apparent deterioration in Fixed-Pattern Noise (FPN) and thermal noise.

50 citations


"A 12-bit, 2.5-bit/Phase Column-Para..." refers background in this paper

  • ...In addition, the postlayout results of the ADC designed in 5.6-μm pitch are presented with an FoM of 0.037 pJ/conversion-step....

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  • ...The obtained figure of merit (FoM) (Walden) of the stand-alone ADC is 0.31 pJ/conversion-step....

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  • ...The column ADC with the relaxed second stage consumes 256 μW of power, resulting in an FoM [15] of 0....

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  • ...The power consumed by the ADC is 435 μW, resulting in the FoM of 0.31 pJ/conversion-step....

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  • ...The column ADC with the relaxed second stage consumes 256 μW of power, resulting in an FoM [15] of 0.037 pJ/conversion-step....

    [...]