Proceedings ArticleDOI

# A low power low latency comparator for ramp ADC in CMOS imagers

22 May 2016-pp 1466-1469

TL;DR: The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator to reduce the latency and increase the power consumption.

AbstractA low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated in UMC 180 nm CMOS technology. Circuit consumes total power of 4.289 μW while operating at the clock frequency of 20 MHz. Measurement results proved that the designed comparator requires maximum of three clock cycles to perform switching for the input range 250–850 mV.

##### Citations
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Journal ArticleDOI
TL;DR: The experiment shows that the compression of 86.2% can be achieved using the threshold of two intensity levels and the compressed image can be reconstructed with the PSNR of 45.87 dB.
Abstract: A superpixel based on-chip compression is proposed in this paper. Pixels are compared in spatial domain and the pixels with similar characteristics are grouped to form the superpixels. Only one pixel corresponding to each superpixel is read to achieve the compression. The on-chip compression circuit is designed and simulated in UMC 180 nm CMOS technology. For 70% compression, the proposed design results in about 33% power saving. The reconstruction of the compressed image is performed off-chip using bilinear interpolation. Further, two enhancement approaches are developed to improve the output image quality. The first approach is based on wavelet decomposition whereas the second approach uses a deep convolutional neural network. The proposed reconstruction technique takes two orders of magnitude lesser time as compared to the state-of-the-art technique. On an average, it results in peak signal to noise ratio (PSNR) and structural similarity index measure values of 30.999 and 0.9088 dB, respectively, for 70% compression in natural images. On the other hand, the best values observed from the existing approaches for the two metrics are 28.634 and 0.8115 dB, respectively. Further, the proposed technique is found useful for thermal image compression and reconstruction. The experiment shows that the compression of 86.2% can be achieved using the threshold of two intensity levels and the compressed image can be reconstructed with the PSNR of 45.87 dB.

7 citations

Journal ArticleDOI
TL;DR: The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption and the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate.
Abstract: A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/−0.5 LSB and +0.8/−0.9 LSB, respectively. The ADC consumes 435- $\mu \text{W}$ of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 $\mu \text{m}$ show that it is suitable for column-parallel readout in CMOS image sensors.

4 citations

### Cites methods from "A low power low latency comparator ..."

• ...The ADC uses a double-tail comparator, where the preamplifier is biased with a constant current source for high gain and low offset [9]....

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Journal ArticleDOI
TL;DR: A low-power readout using reconfigurable cyclic ADC for CMOS image sensors is proposed, which reduces the total number of pixels to be read by taking advantage of pixel correlation, resulting in power saving and improvement in FoM.
Abstract: In this paper, a low-power readout using reconfigurable cyclic ADC for CMOS image sensors is proposed. It reduces the total number of pixels to be read by taking advantage of pixel correlation. The required number of ADC operations is reduced, resulting in power saving. In contrast to the existing pixel correlation-based approaches, which focus only on the intensity differences, in the proposed method, the polarity of the differences is also taken into account. It helps in preserving fine edges representing features such as texture. The discarded or unread pixels are interpolated on-chip while reconfiguring the ADC input range according to the interpolation step size. Furthermore, this reduces the number of ADC conversion cycles by 25% to 50% for interpolation steps of 16 LSB and 64 LSBs, respectively. The ADC is designed and fabricated in UMC 180-nm CMOS technology, and the proposed method is verified for standard test images. The reconstructed images incorporating ADC non-linearities result in average Pratt’s FoM values of 0.88, 0.86, and 0.81 for 60%, 70%, and 74% compression, respectively. The corresponding best values achieved by the existing approaches are 0.86, 0.80, and 0.77, respectively. The improvement in FoM is observed due to the consideration of polarity information. The proposed technique results from 33% to 50% power saving for 80% compression in $512\times512$ image, using reconfigurable ADC. Therefore, it is suitable for a power efficient CMOS sensor design.

3 citations

• ...component efficient using circuit level techniques [2]–[4]....

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Proceedings ArticleDOI
27 Dec 2018
TL;DR: A low-power, high-speed on-chip compression and reconstruction technique that takes the advantage of correlation between the consecutive pixels and reduces the total number of pixels to be read, which results in power saving.
Abstract: A low-power, high-speed on-chip compression and reconstruction technique is proposed in this paper. It takes the advantage of correlation between the consecutive pixels and reduces the total number of pixels to be read. The discarded pixels are interpolated on-chip using the proposed interpolation circuit. This reduces the total number of A/D conversions and hence results in power saving. The algorithm is verified for standard Lena image and about 5 dB better PSNR is observed for 20%- 90% compression, as compared to the existing techniques. Moreover, a promising performance is achieved on thermal image applications. The circuit is designed and simulated in AMS 350 nm OPTO process. For 57% compression, about 45% power saving in readout of the image sensor is observed.

3 citations

Journal ArticleDOI
TL;DR: The proposed compressive acquisition technique for on-array image compression is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.
Abstract: A compressive acquisition technique for on-array image compression is proposed in this paper. It capitalizes on representation ability of accumulated spatial gradients of the acquired scene. The local variations inferred from strength of the accumulated gradients are used as cues to vary number of samples read through the image sensor readout. Such sampling enables the reconstruction using traditional interpolation techniques with desired quality. The proposed method is first verified using MATLAB simulations, where on an average, a compression of 87% is achieved, for a threshold of 40 intensity levels. The images are reconstructed using nearest neighbour interpolation (NNI) method which results in a mean peak signal to noise ratio (PSNR) value of 29.09 dB. The reconstructed images are further enhanced using deep convolutional neural network, which improves the PSNR to 32.46 dB. The biggest advantage of the proposed technique is low-complex hardware design. As a proof of concept, a hardware implementation of the technique is performed using discrete components. Pixel intensity values of standard images are converted into analog voltages using a data acquisition system and mapped in the input voltage range of 1.5 V −5.5 V. For a threshold of 3.8 V, the compression of 81% - 83% is observed for the considered images. The proposed technique is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.

2 citations

### Cites methods from "A low power low latency comparator ..."

• ...To optimize the performance of imager, various architecture level techniques [2]–[4] and circuit-level techniques [5]–[7] are reported in literature....

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##### References
More filters
Journal ArticleDOI
TL;DR: A column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors and error correction scheme to improve the linearity is proposed.
Abstract: This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 times 240 pixels has been fabricated with a 0.35-mum CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mus , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.

112 citations

### "A low power low latency comparator ..." refers background or methods in this paper

• ...This limitation can be overcome using accelerated ramp [2], simultaneous conversion [3], and multiple stage architectures [4, 5]....

[...]

• ...In addition, the components resulting in dynamic power such as the ramp generator and the counter are generally implemented in the chip level [4, 5]....

[...]

Proceedings ArticleDOI
, Yang Xu1
03 Apr 2012
TL;DR: By implementing a high-gain column-level amplifier and CMS technique together with an in-pixel buried-channel source follower (BSF) [6], the TRN level can be reduced even further.
Abstract: For low-light-level imaging, the performance of a CMOS image sensor (CIS) is usually limited by the temporal readout noise (TRN) generated from its analog readout circuit chain. Although a sub-electron TRN level can be achieved with a high-gain pixel-level amplifier, the pixel uniformity is highly impaired up to a few percent by its open-loop amplifier structure [1]. The TRN can be suppressed without this penalty by employing either a high-gain column-level amplifier [2] or a correlated multiple sampling (CMS) technique [3–5]. However, only 1-to-2 electron TRN level has been reported with the individual use of these approaches [2–5], and the low-frequency noise of the in-pixel source follower i.e. 1/fand RTS noise is a further limitation. Therefore, by implementing a high-gain column-level amplifier and CMS technique together with an in-pixel buried-channel source follower (BSF) [6], the TRN level can be reduced even further.

65 citations

### "A low power low latency comparator ..." refers background in this paper

• ...Ramp based ADCs are most widely used in low noise CMOS imagers [1]....

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Proceedings ArticleDOI

18 Jun 2007
TL;DR: A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture that has a 3.3times shorter conversion time than classic single-Slope architecture with equal power.
Abstract: A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.

46 citations

### "A low power low latency comparator ..." refers background or methods in this paper

• ...This limitation can be overcome using accelerated ramp [2], simultaneous conversion [3], and multiple stage architectures [4, 5]....

[...]

• ...In addition, the components resulting in dynamic power such as the ramp generator and the counter are generally implemented in the chip level [4, 5]....

[...]

Proceedings ArticleDOI
23 May 2005
TL;DR: Using this comparator design, the power consumption of column-level single-slope ADC of a CMOS imager can be reduced significantly.
Abstract: In this paper, a 1.8 V 3.2 /spl mu/W comparator is presented. It features a hybrid offset compensation scheme and achieves over 60 dB gain with an input offset below 150 /spl mu/V. The comparator is designed in a 0.18 /spl mu/m CMOS process and is specifically designed to be used as the key component of a column-level single-slope ADC of a CMOS imager. This ADC architecture is attractive because of its low noise, but so far this has come at the price of a relatively high power consumption. Using this comparator design, the power consumption of column-level single-slope ADC can be reduced significantly.

25 citations

### "A low power low latency comparator ..." refers background or methods in this paper

• ...Parameters [6] Proposed Proposed Proposed (1) (2) (3)...

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• ...When the comparator is used in a ramp ADC, the offset voltage can be removed using a suitable offset reduction technique while the timing offset can be corrected in the digital domain [6]....

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• ...Measurement results shows an improvement of 75% in latency compared to [6] with an increase in power consumption of 34%....

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• ...Table 1 shows the performance comparison of the proposed comparator with the comparator reported in [6]....

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• ...(a) Preamplifier (b) Regenerative latch [6] (c) SR Latch (Dynamic bias technique)...

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Journal ArticleDOI
TL;DR: A new simultaneous multislope analog-digital converter architecture suitable for array implementations in, e.g., CMOS image sensors (CISs), which is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry.
Abstract: This brief presents a new simultaneous multislope analog-digital converter (ADC) architecture suitable for array implementations in, e.g., CMOS image sensors (CISs). The simplest implementation is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry. Measurements have been performed on a custom made CIS which implements parts of the proposed ADC. The measurements show good linearity and verify the concept of the new architecture

18 citations

### "A low power low latency comparator ..." refers methods in this paper

• ...This limitation can be overcome using accelerated ramp [2], simultaneous conversion [3], and multiple stage architectures [4, 5]....

[...]