Proceedings ArticleDOI
A low power low latency comparator for ramp ADC in CMOS imagers
Amandeep Kaur,Mukul Sarkar +1 more
- pp 1466-1469
TLDR
The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator to reduce the latency and increase the power consumption.Abstract:
A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated in UMC 180 nm CMOS technology. Circuit consumes total power of 4.289 μW while operating at the clock frequency of 20 MHz. Measurement results proved that the designed comparator requires maximum of three clock cycles to perform switching for the input range 250–850 mV.read more
Citations
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Content Driven On-Chip Compression and Time Efficient Reconstruction for Image Sensor Applications
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A Power Efficient Image Sensor Readout With On-Chip $\delta$ -Interpolation Using Reconfigurable ADC
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A low kickback noise and low power dynamic comparator
TL;DR: In this paper, a low kickback noise and low power dynamic comparator is proposed, which uses the current recycling approach to save power and proposes two noise reduction techniques using only two additional switches.
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