Mathematica--A System for Doing Mathematics by Computer.

The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup/tear-down procedures We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs

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Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the edge of congestion. Typical applications are in the area of multi-media processing. We consider a mesh-based networks on chip (NoC) architecture, and we explore the assignment of cores to mesh cross-points so that the traffic on links satisfies bandwidth constraints. A single-path deterministic routing between the cores places high bandwidth demands on the links. The bandwidth requirements can be significantly reduced by splitting the traffic between the cores across multiple paths. In this paper, we present NMAP, a fast algorithm that maps the cores onto a mesh NoC architecture under bandwidth constraints, minimizing the average communication delay. The NMAP algorithm is presented for both single minimum-path routing and split-traffic routing. The algorithm is applied to a benchmark DSP design and the resulting NoC is built and simulated at cycle accurate level in SystemC using macros from the /spl times/pipes library. Also, experiments with six video processing applications show significant savings in bandwidth and communication cost for NMAP algorithm when compared to existing algorithms.

/pdf/bandwidth-constrained-mapping-of-cores-onto-noc-av00hnba6r.pdf

Bandwidth-constrained mapping of cores onto NoC architectures

We are witnessing a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems. Current integrated circuits contain several processing cores, and even relatively simple systems, such as cellular telephones, behave as multiprocessors. Moreover, many electronic systems consist of heterogeneous components and they require efficient on-chip communication. In the last few years, multiprocessing platforms have been developed to address high performance computation, such as image rendering. Examples are Sony’s emotion engine [OKA] and IBM’s cell chip [PHAM] where on-chip communication efficiency is key to the overall system performance.

Networks on chip

This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitives to build complex architectures from basic components. This bottom up approach allows design-architects to explore efficient custom solutions with best performances. This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. The system specifications are represented as a virtual architecture described in a SystemC-like model and annotated with a set of configuration parameters. Our component-based design environment provides automatic wrapper-generation tools able to synthesize hardware interfaces, device drivers, and operating systems that implement a high-level interconnect API. This approach, experimented over a VDSL system, shows a drastic design time reduction without any significant efficiency loss in the final circuit.

/pdf/component-based-design-approach-for-multicore-socs-2oang28hzz.pdf

Component-based design approach for multicore SoCs

In the near future, Multi-Processor Systems-on-Chip (MPSoC) will become the main thrust driving the evolution of integrated circuits. MPSoCs introduce new challenges, mainly due to growing communication through their interconnect structure. Current electrical interconnects will face hard challenges to overcome such data flows. Integrated optical interconnect is a potential technological improvement to reduce these problems. The main contributions of this paper are i) the optical network integration in a system-level MPSoC platform and ii) the quantitative evaluation of optical interconnect for MPSoC design using a multimedia application.

/pdf/system-level-assessment-of-an-optical-noc-in-an-mpsoc-113f3nkefc.pdf

System level assessment of an optical NoC in an MPSoC platform

A high-level, component-based methodology and design environment for multiprocessor SoC architectures reduces design time without significant efficiency loss in the final circuit. This design environment provides tools for automatic wrapper generation that synthesize hardware interfaces, device drivers, and operating systems implementing high-level interconnect APIs.

Multiprocessor SoC platforms: a component-based design approach

State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising paradigms for the design of such next generation Multi-Processors System on Chip (MPSoC). They enable significantly increased bandwidth, increased immunity to electromagnetic noise, decreased latency, and decreased power. Therefore, defining new architectures taking advantage of optical interconnects represents today a key issue for MPSoC designers. Moreover, new design methodologies, considering the design constraints specific to these architectures are mandatory. In this paper, we present a contention-free new architecture based on optical network on chip, called Optical Ring Network-on-Chip (ORNoC). We also show that our network scales well with both large 2D and 3D architectures. For the efficient design, we propose automatic wavelength-/waveguide assignment and demonstrate that the proposed architecture is capable of connecting 1296 nodes with only 102 waveguides and 64 wavelengths per waveguide.

https://hal.inria.fr/inria-00618600/document

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology

The demands of increasingly complex embedded systems and associated performance computations have resulted in the development of heterogeneous computing architectures that often integrate several types of processors, analog and digital electronic components, and mechanical and optical componentsall on a single chip. As a result, now the most prominent challenge for the design automation community is to efficiently plan for such heterogeneity and to fully exploit its capabilities. A compilation of work from internationally renowned authors, Model-Based Design for Embedded Systems elaborates on related practices and addresses the main facets of heterogeneous Model-Based Design for embedded systems, including the current state of the art, important challenges, and the latest trends. Focusing on computational models as the core design artifact, this book presents the cutting-edge results that have helped establish Model-Based Design and continue to expand its parameters.The book is organized into three sections: Real-Time and Performance Analysis in Heterogeneous Embedded Systems, Design Tools and Methodology for Multiprocessor System-on-Chip, and Design Tools and Methodology for Multidomain Embedded Systems. The respective contributors share their considerable expertise on the automation of design refinement and how to relate properties throughout this refinement while enabling analytic and synthetic qualities. They focus on multi-core methodological issues, real-time analysis, and modeling and validation, taking into account how optical, electronic, and mechanical components often interface. Model-Based Design is emerging as a solution to bridge the gap between the availability of computational capabilities and our inability to make full use of them yet. This approach enables teams to start the design process using a high-level model that is gradually refined through abstraction levels to ultimately yield a prototype. When executed well, Model-Based Design encourages enhanced performance and quicker time to market for a product. Illustrating a broad and diverse spectrum of applications such as in the automotive aerospace, health care, consumer electronics, this volume provides designers with practical, readily adaptable modeling solutions for their own practice.

/pdf/model-based-design-for-embedded-systems-421ay29szc.pdf

Gabriela Nicolescu

Papers

Component-based design approach for multicore SoCs

System level assessment of an optical NoC in an MPSoC platform

Multiprocessor SoC platforms: a component-based design approach

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology

Model-Based Design for Embedded Systems