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Amir H. Ashouri

Researcher at University of Toronto

Publications -  18
Citations -  446

Amir H. Ashouri is an academic researcher from University of Toronto. The author has contributed to research in topics: Compiler & Optimizing compiler. The author has an hindex of 9, co-authored 17 publications receiving 305 citations. Previous affiliations of Amir H. Ashouri include Polytechnic University of Milan.

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Journal ArticleDOI

A Survey on Compiler Autotuning using Machine Learning

TL;DR: A recent survey as discussed by the authors summarizes and classifies the recent advances in using machine learning for the compiler optimization field, particularly on the two major problems of (1) selecting the best optimizations, and (2) phase-ordering of optimizations.
Journal ArticleDOI

COBAYN: Compiler Autotuning Framework Using Bayesian Networks

TL;DR: The proposed framework is based on the application characterization done dynamically by using independent microarchitecture features and Bayesian networks and demonstrates 4 × and 3 × speedup, respectively, on cBench and Polybench in terms of exploration efficiency given the same quality of the solutions generated by the random iterative compilation model.
Journal ArticleDOI

A Survey on Compiler Autotuning using Machine Learning

TL;DR: This survey summarizes and classifies the recent advances in using machine learning for the compiler optimization field, particularly on the two major problems of selecting the best optimizations, and the phase-ordering of optimizations.
Journal ArticleDOI

MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning

TL;DR: This article proposes an automatic optimization framework called MiCOMP, which Mi tigates the Com piler P hase-ordering problem, and performs phase ordering of the optimizations in LLVM’s highest optimization level using optimization sub-sequences and machine learning.
Proceedings ArticleDOI

A Bayesian network approach for compiler auto-tuning for embedded processors

TL;DR: A machine-learning approach for reducing the cost of the compiler auto-tuning phase and to speedup the application performance in embedded architectures based on an application characterization done dynamically with microarchitecture independent features and based on the usage of Bayesian Networks.