A
Amrutur Bharadwaj
Researcher at Indian Institute of Science
Publications - 7
Citations - 113
Amrutur Bharadwaj is an academic researcher from Indian Institute of Science. The author has contributed to research in topics: Programmable Interrupt Controller & Clock rate. The author has an hindex of 4, co-authored 7 publications receiving 89 citations.
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Proceedings ArticleDOI
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions
Keshavan Varadarajan,S. K. Nandy,Vishal Sharda,Amrutur Bharadwaj,Ravi Iyer,Srihari Makineni,Donald Newell +6 more
TL;DR: Through simulation studies, this paper establishes the superiority of molecular cache (caches built as aggregations of molecules) that offers a 29% power advantage over that of an equivalently performing traditional cache.
Journal ArticleDOI
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks
TL;DR: Results show that the cumulative distribution function of leakage current of ISCAS'85 circuits can be predicted accurately with the error in mean and standard deviation, compared to Monte Carlo-based simulations, being less than 1% and 2% respectively across a range of voltage and temperature values.
Proceedings ArticleDOI
CORNET: A Co-Simulation Middleware for Robot Networks
Srikrishna Acharya,Amrutur Bharadwaj,Yogesh Simmhan,Aditya Gopalan,Parimal Parag,Himanshu Tyagi +5 more
TL;DR: CorNET as mentioned in this paper is a co-simulation middleware for applications involving multi-robot systems like a network of Unmanned Aerial Vehicle (UAV) systems, which integrates existing tools to simulate flight dynamics and network related aspects.
Proceedings ArticleDOI
A RISC-V ISA compatible processor IP for SoC
TL;DR: This work focusses on a new processor for a System on Chip that has a 32-bit, 5-stage pipelined processor, memory subsystem with virtual memory support, interrupt controller, memory error control module, and UART.
Proceedings ArticleDOI
A RISC-V ISA Compatible Processor IP
TL;DR: A high-performance general-purpose processor system, based on open source RISC-V instruction set architecture, that has a 32-bit 5-stage pipeline core with separate 8 KB I-Cache and D-Cache, and supports virtual memory system.