Proceedings ArticleDOI
A RISC-V ISA compatible processor IP for SoC
Suseela Budi,Pradeep Gupta,Kuruvilla Varghese,Amrutur Bharadwaj +3 more
- pp 1-5
TLDR
This work focusses on a new processor for a System on Chip that has a 32-bit, 5-stage pipelined processor, memory subsystem with virtual memory support, interrupt controller, memory error control module, and UART.Abstract:
The emergence of System-on-Chip technology has brought in opportunities in the form of reduced cycle time, superior performance and time-to-market considerations. Our work focusses on a new processor for a System on Chip. The system has a 32-bit, 5-stage pipelined processor, memory subsystem with virtual memory support, interrupt controller, memory error control module, and UART. The processor is based on RISC-V ISA. It supports Integer, Multiply, and Atomic instructions. Memory subsystem includes split caches and translation lookaside buffers. Interrupt controller supports four levels of preemptive priority and preemption can be programmed for individual interrupts. Memory error control module provides single error correction and double error detection for main memory. Wishbone B.3 bus standard is adopted as on-chip bus protocol. The design is implemented on Virtex-7 (XC7VX485tffg1761-2) board and achieves a peak clock frequency of 100MHz.read more
Citations
More filters
Journal ArticleDOI
Blockchain in internet-of-things: a necessity framework for security, reliability, transparency, immutability and liability
TL;DR: The wide-ranging Blockchain technology is discovered and it's perspective with respect to ‘internet-of-things’ controlled nodes is studied and illustrates that the established method is functional in test-bed environment.
Proceedings ArticleDOI
Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGAs
TL;DR: This paper presents a modular hybrid memory system for a lightweight RISC-V based MPSoC architecture, which consists of a global scratchpad on-chip shared memory for both instruction and data for the purpose of communication and synchronization between the processing elements.
Proceedings ArticleDOI
Reconfigurable RISC-V Secure Processor And SoC Integration
TL;DR: An austere RISC-V core processor with RV32I subset instruction is deemed as a master device to cooperate with an AES cryptographic engine in an SoC, due to its openness and flexibility.
Proceedings ArticleDOI
A RISC-V ISA Compatible Processor IP
TL;DR: A high-performance general-purpose processor system, based on open source RISC-V instruction set architecture, that has a 32-bit 5-stage pipeline core with separate 8 KB I-Cache and D-Cache, and supports virtual memory system.
Journal ArticleDOI
A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications
TL;DR: A new DMR based reconfigurable quad-core RV32IM processor architecture is proposed for fault-tolerant applications that reduces the resource overhead and makes the processor energy-efficient by optimally using all four processor cores to provide fault-Tolerant results.
References
More filters
Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Cache Memories
TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.
ReportDOI
The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0
TL;DR: RISC-V (pronounced risk-five) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which it is hoped will become a standard open architecture for industry implementations.
The RISC-V Instruction Set Manual Volume 2: Privileged Architecture Version 1.7
TL;DR: This document describes the RISC-V privileged architecture, which covers all aspects of Risc-V systems beyond the user-level ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices.
Proceedings ArticleDOI
A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC
Ckristian Duran,D. Luis Rueda,Giovanny Castillo,Anderson Agudelo,Camilo Rojas,Luis Chaparro,Harry Hurtado,Juan Eduardo Romero,Wilmer Ramirez,Hector Gomez,Javier Ardila,Luis E. G. Rueda,Hugo Hernandez,Jose Amaya,Elkim Roa +14 more
TL;DR: This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process and has a reduced footprint of 798μm×484μm.