https://engineering.purdue.edu/~ee650/downloads/NBTI-Ref1.pdf

A comprehensive model of PMOS NBTI degradation

Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various locations inside a chip. We demonstrate this concept of circuit failure prediction for a dominant PMOS aging mechanism induced by negative bias temperature instability (NBTI). NBTI-induced PMOS aging slows down PMOS transistors over time. As a result, the speed of a chip can significantly degrade over time and can result in delay faults. The traditional practice is to incorporate worst-case speed margins to prevent delay faults during system operation due to NBTI aging. A new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost. Simulation results using 90nm and 65nm technologies demonstrate that this technique can significantly improve system performance by enabling close to best-case design instead of traditional worst-case design.

Circuit Failure Prediction and Its Application to Transistor Aging

The tunneling current from a scanning tunneling microscope was used to image and dissociate single O{sub 2} molecules on the Pt(111) surface in the temperature range of 40 to 150K. After dissociation, the two oxygen atoms are found one to three lattice constants apart. The dissociation rate as a function of current was found to vary as I{sup 0.8{plus_minus}0.2} , I{sup 1.8{plus_minus}0.2} , and I{sup 2.9{plus_minus}0.3} for sample biases of 0.4, 0.3, and 0.2V, respectively. These rates are explained using a general model for dissociation induced by intramolecular vibrational excitations via resonant inelastic electron tunneling. {copyright} {ital 1997} {ital The American Physical Society}

Single Molecule Dissociation by Tunneling Electrons

Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the degradation of NBTI in both static and dynamic operations. Model scalability and generality are comprehensively verified with experimental data over a wide range of process and bias conditions. By implementing the new model into SPICE for an industrial 90nm technology, key insights are obtained for the development of robust design solutions: (1) the most effective techniques to mitigate the NBTI degradation are V/sub DD/ tuning, PMOS sizing, and reducing the duty cycle; (2) an optimal V/sub DD/ exists to minimize the degradation of circuit performance; (3) tuning gate length or the switching frequency has little impact on the NBTI effect; (4) a new switching scenario is identified for worst case timing analysis during NBTI stress.

Modeling and minimization of PMOS NBTI effect for robust nanometer design

https://www.iue.tuwien.ac.at/pdf/ib_2011/JB2011_Grasser_5.pdf

Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

A quantitative model is developed for the first time, that comprehends all the unique characteristics of NBTI degradation. Several models are critically examined to develop a reaction/diffusion based modeling framework for predicting interface state generation during NBTI stress. NBTI degradation is found to be dominated by diffusion of neutral atomic and molecular hydrogen related defects. Additionally, the presence of hydrogen gettering sites such as unsaturated grain bound- aries significantly enhance NBTI degradation, whereas hydrogen sources reduce NBTI degradation. The model also suggests the possible mechanisms for saturation. The model is calibrated over a range of stress temperatures and voltages. The model captures recovery, experimental delay and frequency effects successfully.

A comprehensive framework for predictive modeling of negative bias temperature instability

We describe a quantitative relationship between I/sub D/ and V/sub T/ driven NBTI specifications Mobility degradation is shown to be a significant (/spl sim/40%) contributor to I/sub D/ degradation We report for the first time, degradation in gate-drain capacitance (C/sub GD/) due to NBTI The impact of this C/sub GD/ degradation on circuit performance is quantified for both digital and analog circuits We find that C/sub GD/ degradation has a greater impact on the analog circuit studied than the digital circuit We demonstrate that there is an optimum operating voltage that balances NBTI degradation against transistor voltage headroom Further, a numerical model based on the reaction-diffusion theory has been developed, which is found to satisfactorily describe degradation, recovery and post-recovery response to stress

NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]

We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Furthermore, we show that the Static Noise Margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.

Impact of negative bias temperature instability on digital circuit reliability

Negative bias temperature instability (NBTI) is known to exhibit significant recovery upon removal of the gate voltage The process dependence of this recovery behavior is studied by using the time slope (n) as the monitor We observe a systematic variation of n with oxide thickness, nitrogen concentration, and fluorine implantation Incorporation of the material dependence of the diffusivity within the reaction-diffusion (R-D) framework captures the observed trends The consequences of this modification are (a) diffusion limitation is shown to arise from diffusion in poly-Si, rather than oxide, (b) a plausible explanation for low-voltage stress induced leakage current (LV-SILC) naturally appears Important findings are (a) NBTI degradation remains significant at high frequencies, (b) numerical simulations at moderate frequencies can be used to predict circuit impact in the GHz regime, (c) high frequency operation can be modeled as a lower effective DC stress

Anand T. Krishnan

Papers

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

A comprehensive framework for predictive modeling of negative bias temperature instability

NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]

Impact of negative bias temperature instability on digital circuit reliability

Material dependence of hydrogen diffusion: implications for NBTI degradation