BIST is a viable approach to test today's digital systems. Constraints, such as power, noise, area overhead, and others, limit the possibilities of parallel BIST execution in complex VLSI devices. This paper presents a BIST scheduling process that takes into consideration such constraints, and introduces a new BIST control methodology, that implements the BIST schedule with a highly modular architecture. In fact, due to the uniformity of interface, the BIST control elements are independent of the BIST scheme used in the embedded blocks of a device. This BIST control architecture can provide block level diagnostic information. >

A distributed BIST control scheme for complex VLSI devices

Online learning algorithms often have to operate in the presence of concept drift (i.e., the concepts to be learned can change with time). This paper presents a new categorization for concept drift, separating drifts according to different criteria into mutually exclusive and nonheterogeneous categories. Moreover, although ensembles of learning machines have been used to learn in the presence of concept drift, there has been no deep study of why they can be helpful for that and which of their features can contribute or not for that. As diversity is one of these features, we present a diversity analysis in the presence of different types of drifts. We show that, before the drift, ensembles with less diversity obtain lower test errors. On the other hand, it is a good strategy to maintain highly diverse ensembles to obtain lower test errors shortly after the drift independent on the type of drift, even though high diversity is more important for more severe drifts. Longer after the drift, high diversity becomes less important. Diversity by itself can help to reduce the initial increase in error caused by a drift, but does not provide the faster recovery from drifts in long-term.

/pdf/the-impact-of-diversity-on-online-ensemble-learning-in-the-5apps5tlop.pdf

The Impact of Diversity on Online Ensemble Learning in the Presence of Concept Drift

Motivation: The Basic Local Alignment Search Tool (BLAST) is one of the most widely used bioinformatics tools. The widespread impact of BLAST is reflected in over 53 000 citations that this software has received in the past two decades, and the use of the word ‘blast’ as a verb referring to biological sequence comparison. Any improvement in the execution speed of BLAST would be of great importance in the practice of bioinformatics, and facilitate coping with ever increasing sizes of biomolecular databases.

Results: Using a general-purpose graphics processing unit (GPU), we have developed GPU-BLAST, an accelerated version of the popular NCBI-BLAST. The implementation is based on the source code of NCBI-BLAST, thus maintaining the same input and output interface while producing identical results. In comparison to the sequential NCBI-BLAST, the speedups achieved by GPU-BLAST range mostly between 3 and 4.

Availability: The source code of GPU-BLAST is freely available at http://archimedes.cheme.cmu.edu/biosoftware.html.

Contact: sahinidis@cmu.edu

Supplementary information:Supplementary data are available at Bioinformatics online.

Gpu-blast

It is shown how to construct a general linear hybrid cellular automaton (CA) such that it has a maximum length cycle, and how the aliasing properties of such automata compare with linear feedback shift registers (LFSRs) when used as signature analyzers The construction is accomplished by formally demonstrating the isomorphism which binds this kind of CA to the LFSRs Consequently, these CAs can be analyzed as linear machines Linear algebraic techniques are then applied appropriately for the transformations, and a useful search algorithm is developed which, given an irreducible characteristic polynomial, finds a corresponding linear hybrid automaton Such CAs are tabulated for all irreducible and primitive polynomials up to degree 16, plus a selection of others of higher degree The behavior of a linear hybrid CA and that of its corresponding LFSR are similar-that is, they have the same cycle structure and only relabel the states The aliasing properties, when they are used as signature analyzers, remain unchanged >

The analysis of one-dimensional linear cellular automata and their aliasing properties

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.


Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly 
Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence 
Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products 
Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes



Table of Contents


Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

Electronic Design Automation: Synthesis, Verification, and Test

Parallel and distributed systems

A low power consumption system for monitoring time of use of appliance incorporates a controller and a temperature sensor that is activated by the controller at intervals of X minutes to determine the temperature of the sensor. The sensed temperature is then compared with a threshold temperature and a counter is turned ON to accumulate time if the sensed temperature is at the desired level or turned OFF when the sensed temperature is not in the desired range. The counter remains in its ON or OFF position until the sensed temperature causes the counter to shift to the opposite position to the one it is in at that time. The counter receives oscillations from the oscillator which is continuously operating and only counts those oscillations when the counter is set in the ON position.

Time monitoring appliance

A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described. For test generation, the scheme uses the exhaustive test technique. For output data evaluation the scheme uses both time and space compactors. Linear space compaction is performed using a multiple-input linear feedback shift register (MISR). For time compaction, nonlinear compaction (count-based) enhanced by the output data modification (ODM) technique is used. Space compaction is further enhanced by using a bidirectional MISR. >

An effective BIST scheme for ROM's

An iterative technique for computing the exact probability of aliasing for any linear feedback signature register (i.e. characterized by any feedback polynomial, for any constant probability of error, and for any test length) is proposed. The technique is also applicable to a more general model of the aliasing problem wherein the probability of error may vary with each output bit. The complexity of the technique enables registers of lengths of interest in practice, e.g. 16, to be analyzed readily. >

An iterative technique for calculating aliasing probability of linear feedback signature registers

The authors address space compaction for built-in self-test (BIST). High quality BIST of modern complex VLSI circuits requires that large numbers of internal nodes be monitored during test. Unfortunately, area limitations typically preclude the association of observation latches for all the nodes of interest in the case where these are very numerous. Consequently, the process known as space compaction is increasingly required. A first contribution here is a taxonomy of test data compaction functions for BIST that uses space, time, memory, linearity, and circuit (functional) specificity as attributes. The major contribution is the introduction of a general class of space compactors called programmable space compactors (PSCs). Programmability enables highly effective space compactors to be designed for circuits under test (CUTs) subjected to a specific set of test patterns. The measures of effectiveness used to assess the PSCs are realizability, e.g., area, and error propagation performance. The authors develop a probabilistic error propagation model and propose a technique for selecting an effective PSC given the expected test data from a CUT and a probabilistic characterization of faulty CUT behaviors.

André Ivanov

Papers

Parallel and distributed systems

Time monitoring appliance

An effective BIST scheme for ROM's

An iterative technique for calculating aliasing probability of linear feedback signature registers

Programmable space compaction for BIST